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Instruction Enhancement Programme (IEPs)

1. IEP on ASIC Digital Design Using 180nm PDK (Organizer - ChipIN Centre)

SESSIONInsights into RTL-to-GDSII using Cadence EDA Tools for Digital IC design with a focus on 180nm PDK
DURATION12-Feb-2024 to 16-Feb-2024
MODEHybrid
SESSION RECORDINGS
ChipIN Centre IEP Day 1
Theoretical - SCL session Theoretical - Verilog RTL Coding Guidelines Practical - IEP Folder Structure
ChipIN Centre IEP Day 2
Theoretical - Cadence session Theoretical - CDC, RDC and X-Propagation Theoretical - Linting Practical - Linting hands-on Practical - Simulation hands-on
ChipIN Centre IEP Day 3
Theoretical - Floor Planning Theoretical - Import Design Theoretical - Initial Chip Planning Theoretical - Logic Synthesis Theoretical - Power Planning Theoretical - Timing Constraints Theoretical - Understanding SCL PDK Practical - Clock Tree Synthesis Practical - Floor Planning Practical - Placement Practical - Power Planning Practical - Routing Practical - Synthesis
ChipIN Centre IEP Day 4
Theoretical - CoreEL session Theoretical - Seal Ring and Packaging Theoretical - Timing Analysis Practical - SPICE simulation Practical - Timing Signoff
ChipIN Centre IEP Day 5
Theoretical - DFT Theoretical - SPI Enabled AES IP Core

2. IEP on Memory and In-Memory Computing using SCL 180nm PDK (Organizer - IIT Indore)

SESSIONInsights into CMOS IC Design Flow, Memory IP Design using SRAM and RRAM, Basic and Advanced Operations using In-Memory Computing and Fundamentals of Memory Compiler
DURATION18-Mar-2024 to 22-Mar-2024
MODEHybrid
SESSION RECORDINGS
IIT Indore IEP Day 1
Inaugaration Expert Talk: In-Memory Compute Expert Talk: Semiconductor Nation Expert Talk: PPA Analysis LS-1: Cadence Tools
IIT Indore IEP Day 2
Expert Talk: AI & Automotive Expert Talk: SRAM Design LS-2: Schematic Design
IIT Indore IEP Day 3
Case Study: SRAM Integration Expert Talk: Memory for AI LS-5 (P1): I/O Padding LS-5 (P2): I/O Padding LS-6 (P1): 6T-SRAM LS-6 (P2): 6T-SRAM LS-6 (P3): 6T-SRAM LS-7: Peripheral Circuitry
IIT Indore IEP Day 4
LS-8: RRAM Bitcell LS-9: In-Memory Computing
IIT Indore IEP Day 5
Demo Lab: SRAM Analysis Expert Talk: Embedded Memory Expert Talk: Rad-Hard SRAM

3. Digital India RISC-V (DIR-V) architecture and applications (Organizer - NIELIT Calicut)

SESSIONThe sessions included a well-balanced mix of expert talks, hands-on training, and live demonstrations. Experts from the Shakti team of IIT Chennai, the VEGA team from C-DAC Thiruvananthapuram, and the NIELIT team handled the theory and practical sessions.
DURATION9th-Dec-2024 to 13th-Dec-2024
MODEHybrid
SESSION RECORDINGS
NIELIT Calicut IEP Day 1
Part 1Part 2
NIELIT Calicut IEP Day 2
Part 1Part 2
NIELIT Calicut IEP Day 3
Part 1Part 2
NIELIT Calicut IEP Day 4
Part 1Part 2
NIELIT Calicut IEP Day 5
Part 1Part 2Part 3

4. IEP on ASIC Analog Design Using 180nm PDK (Hybrid) (Organizer - ChipIN Centre)

SESSIONInsights into Schematic-to-GDSII using Cadence and Siemens EDA Tools for Analog IC design with a focus on 180nm PDK
DURATION03-Feb-2025 to 07-Feb-2025
MODEHybrid
SESSION RECORDINGS
ChipIN Centre IEP Day 1
Theory Session
ChipIN Centre IEP Day 2
Lab SessionTheory Session
ChipIN Centre IEP Day 3
Lab SessionTheory Session
ChipIN Centre IEP Day 4
Lab SessionTheory Session
ChipIN Centre IEP Day 5
Lab Session

5. IEP on Standard Cell Design, Characterization, and Synthesis using SCL 180nm PDK (Organizer - PES University, Bangalore)

SESSIONInsight into Standard Cell Circuit Design, Layout Design, Characterization, and Synthesis using the Cadence EDA tool using 180nm PDK
DURATION22-Sept-2025 to 26-Sept-2025
MODEHybrid
SESSION RECORDINGS
PESU Bangalore IEP Day 1
Inauguration NXP Expert Talk ChipIn Expert Talk Hands-on Session
PESU Bangalore IEP Day 2
NXP Expert Talk Hands-on (Part 1) Hands-on (Part 2)
PESU Bangalore IEP Day 3
NXP Expert Talk Layout Design 1 Layout Design 2 Layout Design 3
PESU Bangalore IEP Day 4
Layout Design 4 Level Shifter Theory
PESU Bangalore IEP Day 5
Synthesis Talk Design Flow Talk Collaboration Talk Hands-on Final

6. IEP on Digital Design, Logic Synthesis, and Implementation of Algorithms on FPGA (Organizer - Aligarh Muslim University)

SESSIONDesigned to impart advanced training in FPGA-based digital system design with a focus on RTL modelling, custom accelerator development, signal processing, and Python integration
DURATION6-Nov-2025 to 10-Nov-2025
MODEHybrid
SESSION RECORDINGS
AMU IEP Day 1 AMU IEP Day 2 AMU IEP Day 3 AMU IEP Day 4 AMU IEP Day 5

7. IEP on RTL Design and Verification using Verilog (Organizer - Nielit Aurangabad)

SESSIONTo learn & practice RTL Design and verification of complex digital circuits using Verilog HDL
DURATION24-Nov-2025 to 28-Nov-2025
MODEHybrid
SESSION RECORDINGS
Nielit Aurangabad IEP Day 1
Session 1
Nielit Aurangabad IEP Day 2
Session 1 - P1Session 1 - P2Session 2
Nielit Aurangabad IEP Day 3
Session 3 (UVM) Session 3 (SYSTEM VERILOG)
Nielit Aurangabad IEP Day 4
Session 4
Nielit Aurangabad IEP Day 5
Session 5

8. IEP on Design of Signal Processing Accelerators on Zynq System on Chip (SoC) (Organizer - IIIT Delhi)

SESSIONThis program provides comprehensive training on Zynq SoC design, covering fundamental AXI/HLS protocols and practical hardware-software co-design for FFT and Matrix Multiplication.
DURATION21-Dec-2025 to 25-Dec-2025
MODEHybrid
SESSION RECORDINGS
IIIT Delhi IEP Day 1
Lab Session 1Lab Session 2Theory Session 1Theory Session 2
IIIT Delhi IEP Day 2
Lab Session 3Lab Session 4Theory Session 3Theory Session 4
IIIT Delhi IEP Day 3
Lab Session 5Lab Session 6Theory Session 5Theory Session 6
IIIT Delhi IEP Day 4
Lab Session 7Lab Session 8Theory Session 7Theory Session 8
IIIT Delhi IEP Day 5
Lab Session 9Lab Session 10Theory Session 9Theory Session 10

9. IEP on ASIC Design Flow using SCL 180nm Technology (Organizer - Cambridge Institute of Technology, Bangalore )

SESSIONInsights into Design-to-GDSII for ASIC design using Cadence and Siemens EDA Tools with a focus on the latest SCL 180nm PDK.
DURATION23-Feb-2026 to 27-Feb-2026
MODEHybrid
SESSION RECORDINGS
Cambridge IEP Day 1
Session - 1
Cambridge IEP Day 2
Session - 2
Cambridge IEP Day 3
Session - 3
Cambridge IEP Day 4
Session - 4
Cambridge IEP Day 5
Session - 5

10. IEP on Edge AI by IISc & ARM (Organizer - Indian Institute of Science (IISc), Bangalore )

SESSIONThe Instruction Enhancement Program (IEP) will cover modern Arm-based CPU/NPU architectures, Edge AI fundamentals, federated learning, ML edge accelerators, and model-system co-design, along with hands-on tutorials delivered by Arm experts and IISc faculty.
DURATION16-March-2026 to 20-March-2026
MODEHybrid
SESSION RECORDINGS
IISc IEP Day 1
Edge AI Fundamentals-Part I Introduction to Arm Neoverse Compute Subsystem (CSS) and Chiplet Architecture-Arm Introduction to Computer Architecture and Arm Processors - Arm
IISc IEP Day 2
Edge AI Fundamentals - Part II-01 Edge AI Fundamentals - Part II-02
IISc IEP Day 3
AI on Arm and Arm Academic Access - Arm Federated Learning Concepts & Architectures
IISc IEP Day 4
Edge Accelerators & Optimizations Tutorial Systems for Machine Learning - Part I
IISc IEP Day 5
Systems for Machine Learning - Part II

11. IEP on IC Package Design (Organizer - KLE Technological University)

SESSIONTo learn & practice IC packaging technologies, including package types, applications, and electronic package design using Allegro-X APD+. It also covers signal integrity, physical design rules, differential routing, wire bonding, 3D visualization, embedded capacitor setup, SKILL scripting, and concludes with a hands-on IC package design capstone project.
DURATION17-Apr-2026 to 21-Apr-2026
MODEHybrid
SESSION RECORDINGS
KLE Tech. University IEP Day 1
Session 1
KLE Tech. University IEP Day 2
Session 2
KLE Tech. University IEP Day 3
Session 3
KLE Tech. University IEP Day 4
Session 4
KLE Tech. University IEP Day 5
Session 5