Ministry of Electronics and Information Technology
(MeitY)

Theoretical - SCL session Theoretical - Verilog RTL Coding Guidelines Practical - IEP Folder Structure

Theoretical - Cadence session Theoretical - CDC, RDC and X-Propagation Theoretical - Linting Practical - Linting hands-on Practical - Simulation hands-on

Theoretical - Floor Planning Theoretical - Import Design Theoretical - Initial Chip Planning Theoretical - Logic Synthesis Theoretical - Power Planning Theoretical - Timing Constraints Theoretical - Understanding SCL PDK Practical - Clock Tree Synthesis Practical - Floor Planning Practical - Placement Practical - Power Planning Practical - Routing Practical - Synthesis

Theoretical - CoreEL session Theoretical - Seal Ring and Packaging Theoretical - Timing Analysis Practical - SPICE simulation Practical - Timing Signoff

Theoretical - DFT Theoretical - SPI Enabled AES IP Core