2. IEP on Memory and In-Memory Computing using SCL 180nm PDK
(Organizer - IIT Indore)
SESSIONInsights into CMOS IC Design Flow, Memory IP Design using SRAM and RRAM, Basic and Advanced Operations using In-Memory Computing and Fundamentals of Memory Compiler
3. Digital India RISC-V (DIR-V) architecture and applications
(Organizer - NIELIT Calicut)
SESSIONThe sessions included a well-balanced mix of expert talks, hands-on training, and live demonstrations. Experts from the Shakti team of IIT Chennai, the VEGA team from C-DAC Thiruvananthapuram, and the NIELIT team handled the theory and practical sessions.
6. IEP on Digital Design, Logic Synthesis, and Implementation of Algorithms on FPGA
(Organizer - Aligarh Muslim University)
SESSIONDesigned to impart advanced training in FPGA-based digital system design with a focus on RTL modelling, custom accelerator development, signal processing, and Python integration
8. IEP on Design of Signal Processing Accelerators on Zynq System on Chip (SoC)
(Organizer - IIIT Delhi)
SESSIONThis program provides comprehensive training on Zynq SoC design, covering fundamental AXI/HLS protocols and practical hardware-software co-design for FFT and Matrix Multiplication.
