• Establishing State of-the art VLSI Design Laboratory.
• Generation of manpower in VLSI Design area at various levels.
• Instruction Enhancement Program (IEP) for faculties of PIs.
• Workshop involving International Guest Faculty.
• India Chip Program.
• National VLSI website and 7 sites at RCs.

• Primary Objective - To train special manpower in the area of VLSI Design and related software at M.E./M.Tech level (Type-II manpower). In addition to this, generation of Type-III manpower i.e. M.E./M.Tech in other areas of electronics etc. with at least two courses on VLSI design was also undertaken.
• Secondary Objective - Train Type-IV manpower i.e. B.E./B.Tech in electronics etc. with graduate level courses on VLSI Design. However, the program was not only limited to generation of Type-II, III & IV manpower but also generated manpower at Ph.D level in various aspects of VLSI design/microelectronics (Type-I manpower). The establishment of VLSI design laboratories at RCs would also strengthen their academic program.

• Total Outlay: Rs. 49.98 Crores (Actual Expenditure: Rs. 42.24 Crores)
• Duration- 8 Years (2005-2013)
• Implementing Organizations:
  1. 7 Resource Centers (including 5 IITs, IISc Bangalore and CEERI Pilani)
  2. 25 Participating Institutes ( including 16 NITs and 9 other institutions).

• Establishing State of the art VLSI Design Laboratory



VLSI Design Laboratories have been established at 32 institutions equipped with State-of-the art Hardware platforms and Electronics Design Automation (EDA) software. These Labs are being use by students at various levels to undertake design of VLSI circuits. The license of EDA tools like Mentor Graphics & Synopsis have been renewed and the process for renewal of license in case of other EDA tools are in progress.

• Generation of manpower in VLSI Design area at various levels



Under the program the students of RCs and PIs at various levels such as B.Tech, M.Tech and Ph.D where introduced to specialized topic in VLSI design. A model curriculum was also developed. The primary target of the program was to generate substantial number of manpower at M.Tech level having VLSI design as their primary specialization. Students at B.Tech level as well as M.Tech in other area of were also offered electives with VLSI and microelectronics subjects.

The manpower generated under this programme at various levels are depicted in the table below:

Fabrication of twelve chips, 5 in single mode and 7 in multi-mode project wafer (MPW) mode were undertaken for siliconisation of Analog and Digital designs done by students of various RCs and PIs. In the seven MPW chips 32 designs from 16 institutions were integrated together and were prototyped in seven chips. For the seven chips there were seven institutions which acted like an integrator to merge the designs received from other institutors. In this way there was considerable savings in the fabrication cost.

Details of designs done by various RCs and PIs :

Twenty three Instruction Enhancement Programme (IEP) in different topics/area were conducted at various RC/PI locations by Resource centers for the training faculty of Participating Institutions. A total of 654 faculties/Lab Engineers of PIs have been trained through this programme. The details are as below: