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MPW Shuttle-V

28 Designs submitted for Fabrication in MPW Manner at 180nm, SCL Mohali in Jan’ 2026 MPW Shuttle by ChipIN Centre
MPW SHUTTLE - V TO SCL THROUGH CHIPIN CENTRE
Sl.No Silicon Number Institution Name Description of IC
FOUR-METAL PROCESS DESIGN SUBMISSIONS
1C2S0041IITDM KancheepuramMulti-Functional Low-Power ASIC Integrating Neuromorphic ECG Processor and Arithmetic Accelerators
2C2S0069Digital University KeralaSPIMemSlave: Serial Peripheral Interface (SPI) Slave controller with a dual-bank 128×16-bit synchronous memory array
3C2S0109IIT ISM DHANBADLow power analog VLSI memristor emulator and its application in the field of Neuromorphic computing
4C2S0122Dr. Mahalingam College of Engineering and Technology, Pollachi,Design of 16-Channel High-Gain, Low-Power, Low-Noise Neural Signal Amplifier Front End for EEG Monitoring System
5C2S0133NIT JamshedpurDesign and Implementation of a high-speed and low-power uart protocol
6C2S0142Indian Institute of Technology IndoreNOVA-RV: A 32-bit RISC-V based Single-Cycle RISC-V Processor with AXI4-Lite Interface
7C2S0153C-DAC MohaliUniversal Biomedical Filter : a low-power, fully integrated analog signal-conditioning circuit designed for low-frequency physiological signals
8C2S0157UIET, Panjab University, ChandigarhLow-dropout (LDO) regulator
9C2S0162IIT ISM DHANBADLow power analog VLSI neuromorphic crossbar architecture
10C2S0164IIT HyderabadCMOS image sensor architectures for advanced visual perception: a Dynamic Vision Sensor (DVS) for event-based imaging
11C2S0168Kurukshetra UniversityCMOS-based interfacing circuit designed for a resistive-type ammonia gas sensor
12C2S0170Indian institute of Information Technology AllahabadPhysically Unclonable Function (PUF) circuit
13C2S0171Indian institute of Information Technology AllahabadFixed Gain Amplifier (FGA) , Programmable Gain Amplifier
14C2S0193NIT DurgapurDesign and Fabrication of Fully Digital MODEM and FIFO Buffer for ML Enabled RISC-V based i - LoRa SOC for Forest event monitoring
15C2S0194IET DAVV, Indore32-bit RISC-V Processor
16C2S0208NIT PuducherryASIC Implementation of Streamlined Reconfigurable pooling strategy for CNN, Lif nueron and approximate softmax function
SIX-METAL PROCESS DESIGN SUBMISSIONS
17C2S0021Cambridge Institute of Technology, KR Puram, Bangalore4-band Selectable Numerically Controlled Oscillator (NCO)
18C2S0062ChipIN Centre, CDAC BangaloreSPI-enabled SHA-3 IC
19C2S0067Anna University Regional Campus, CoimbatoreMutual Authentication System on Chip Design (MASoC)
20C2S0070Digital University KeralaSingle Inductor Multiple Output (SIMO) DC–DC converter
21C2S0104REVA UNIVERSITYDual x Radix-2 8-point FFT with FIFO using AXI Stream Architecture
22C2S0106BMS College of Engg.A Low Noise Amplifier (LNA) Design
23C2S0120SNS College of Technology, Coimbatoresingle-band Numerically Controlled Oscillator (NCO) operating within the frequency range of 0.55 MHz to 1.0875 MHz
24C2S0154IIT GandhinagarDual Interlocked (DICE) and Double Port-Dual Interlocked (DPDICE) storage cells
25C2S0169MNNIT AllahabadTransmitter Sub-Circuit (Mixer, OPAMP and VCO) and
26C2S0183NIT Arunachal PradeshProgrammable LDO
27C2S0184NIT Arunachal PradeshDigitally controlled Delay cell based pulse shrinking TDC ,Pulse stretching TDC and chain of inverter
28C2S0185NIT Arunachal PradeshDYNAMIC Stress management for power gating in NBTI

Announcement for Tape-out submissions for MPW Shuttle-V at 180nm, SCL Mohali through ChipIN Centre for Participating Institutions under C2S Programme for fabricating them in Jan’ 2026

1.0 ChipIN Centre (C-DAC Bangalore) is now accepting design tape-outs for MPW Shuttle-V at 180nm, SCL Mohali, from Participating Institutions (PIs) under the C2S (Chips to Start-up) Programme for fabricating them in January 2026 as per following timelines.

# MPW Shuttle - V Timelines
1 MPW Shuttle – V Announcement by ChipIN Centre for fabrication of designs at 180nm, SCL Mohali by Participating Institutions (PI) 16th Sept 2025
2 PIs to submit request to ChipIN Centre for obtaining the Silicon number from SCL. 26th Sept 2025
3 ChipIN Centre to provide Silicon number to the PI 03rd Oct 2025
4 Submission of the initial version of design by the PIs to ChipIN Centre as per guidelines of Design Tapeout Submission Form (i.e. Si Number, report on DRC clean, antenna check etc.) 31st Oct 2025
5 ChipIN Centre to provide a Verification Report to PIs for initial version of designs submitted by PIs. 05th Nov 2025
6 PIs to submit the final version of fab-ready design/ GDS to ChipIN Centre addressing the issues, if any, highlighted in the Verification Report. 14th Nov 2025
7 PIs to submit the package GDS and Bonding Table excel for their Designs 18th Nov 2025
8 Submission of designs of PIs by ChipIN Centre to SCL Mohali for fabrication. 30th Nov 2025
9 The designs to go in the fabrication lot at SCL Mohali Jan’ 2026
10 Receiving of fabricated designs in packaged form by the PIs 30th Sept 2026

Design Tapeout Submission Process by Participating Institutions (PIs)
Step 1: Obtaining Silicon Number by PIs
  1. The PIs to send an e-mail to ChipIN Centre to get the Silicon Number with duly filled Silicon_Number_Generation_Form (see attachment) by 26th September 2025. Please go through the Silicon_Numbering_Table (see attachment) for various code details to be used for filling it.
  2. ChipIN Centre to provide Silicon number to the PI.
Step 2: Submission of Design
  1. Participating Institutions (PIs) to provide their design details in the Design Tapeout Submission Form (DTSF) and Process Information Sheet (PIS sheet) for projects intended for tapeout at 180nm, SCL Mohali.
  2. The DTSF provides information on various items, which must be considered when a design is submitted by PI to ChipIN Centre.
  3. All the columns in the PIS sheet must be filled with the drop-in information, wherever provided. At places, where drop-in is not given, designer must write as per the column description only.

    4. Design Tapeout Submission Form (DTSF) (see attachment)
    Process Information Sheet (PIS sheet) (see attachment)
Step 3: Submission of Design
  1. Participating Institutions (PIs) have to provide their design package GDS and Bonding Excel details for packaging their designs at SCL, Mohali.

    2. Package GDS Generation Flow by ChipIN (see attachment)
    Guidelines for Die Information Exchange between End user and Packaging (see attachment)
General Guidelines
1.0 Data Format and Communication:
  1. Acceptable database format is GDSII only.
  2. Complete database must be sent through e-mail to chipin@cdac.in. Do not provide any Google Drive link.
  3. The communication has to be addressed through e-mail at: ChipIN Centre,
    C2S Programme,
    C-DAC Bangalore, Opp. HAL Aeroengine Division,
    Old Madras Road, Byappanahalli,
    Bengaluru - 560 038.
2.0 Layout Grid
  1. Minimum grid size used in the GDSII must be integer multiple of 0.005 µm.
  2. Final GDSII window (including seal ring) must have Bottom left corner at (0,0) coordinate and the Top-Right corner coordinate must be rounded off to closest even number and it should be without any decimal places i.e., 10102 µm or 10100 µm for the case if coordinate comes at 10101.395 µm.
3.0 Design Kit
  1. Do not rename cell names used in cell library.
  2. Do not use library cell name for custom designed cells.
  3. Do not edit standard cell library and I/O library.
4.0 Design Verification
  1. The PIs to provide a clean GDSII database w.r.t. DRC, Density, and Antenna rules.
  2. Before taping out the data, please provide checksum for GDSII file. Save the checksum value and byte count in a file, so that the same can be crosschecked at our end. e.g. cksum C2S0001_01062025_v1.gds 12345678 204 C2S0001_01062025_v1.gds
  3. For GDSII integrity check while data transfer, MD5 checksum is must and need to be provided in addition to checksum so that the same can be crosschecked at our end. For calculating MD5, just open Linux terminal and type: md5sum ‘filename’ e.g. md5sum C2S0001_01062025_v1.gds
  4. GDSII name and Top cell name format:
    • Format: silicon_no_date_version.gds (date format should be ddmmyyyy)
    • Top cell name should be "silicon number" only.
  5. All the reports should be named as GDSII name. For instance:
    • siliconnum_date_version_drc.rpt
    • siliconnum_date_version_drc.summary
    • siliconnum_date_version_ant.rpt
  6. All the columns in the Process Information Sheet (PIS sheet) must be filled with the drop-in information wherever provided. At places where drop-in is not given, designer must write as per the column description only.

5.0 Tapeout Checklist
# Device Related Information Yes/No
1 GDSII database provided
2 Silicon Number with PCI is mandatory. GDSII for this is included in the PDK. (Layer revision block may be placed if space permit)
3 Seal Ring with GND connection inserted?
4 Is DRC along with dummy fill Report clean?
5 Is Antenna along with dummy fill Report clean?
6 Dummy Fill done
7 Grid size 0.005µm used for layout
8 Whether Pads connected till top metal (TOP_M)?
9 Final Chip Origin should be at (0,0) after seal ring insertion.
10 Process Information Sheet duly filled?

6.0 Reports to be Included
1 Final DRC run Reports (Result database including density logs, summary, transcript, runset version)
2 Final Antenna Report (Result database, summary, transcript, runset version)
3 Devices type (or legal devices) used in layout report
4 Stream out log files
5 List of 3rd party IP used (If any with prior approval from SCL)
6 List of SCL IP used (If any with prior approval from SCL)
7 List of all legal layers used before silicon number insertion in Excel Format (Layer Name + layer number + datatype)
8 Coordinate of Silicon number
9 Process Information Sheet (Attached PIS Excel)

7.0 Tape-out and Packaging Related Checklist
# Tape-out and Packaging Related Checklist Please Tick / Specify
1 Mention the Die size including seal ring. Options supported: 2 x 2 mm², 3 x 3 mm², 4 x 4 mm², or 5 x 5 mm²
(No other size is supported in the current tapeout under this program)
For sizes greater than 5 x 5 mm² ChipIN will contact SCL’s PPG.		 Specify 2 x 2 mm² or 3 x 3 mm² or 4 x 4 mm² or 5 x 5 mm²
2 The design should have a seal ring around it. The distance between chip boundary to seal ring should be a minimum of 10µm with DRC Clean.
3 The seal ring is connected to VSS (Ground).
4 No. of pins for Packaging the IC
(Currently no. of pins should not be more than 100 for packaging).		 Specify the No. of Pins
5 Package selected for packaging (Refer Serial No. 8) - Specify the Package Serial Number
6 The minimum pitch between two adjacent bond pads is 90µm for all bond pads.

8.0 Preferred Die Size and plastic packages (Chip-on-Board Packaging Options)
Serial No. Die Size (mm) Package Size (mm) Pin Count Package Lead Pitch (mm) CoB Package Type
12.0 x 2.07.0 x 7.0161.0QFN
23.0 x 3.07.0 x 7.0161.0QFN
32.0 x 2.08.4 x 8.4241.0QFN
43.0 x 3.08.4 x 8.4241.0QFN
53.0 x 3.09.0 x 9.0281.0QFN
62.0 x 2.010.0 x 10.0321.0QFN
73.0 x 3.010.0 x 10.0321.0QFN
82.0 x 2.014.0 x 14.0481.0QFN
93.0 x 3.014.0 x 14.0481.0QFN
102.0 x 2.018.0 x 18.0641.0QFN
113.0 x 3.018.0 x 18.0641.0QFN
124.0 x 4.014.0 x 14.0481.0QFN
135.0 x 5.014.0 x 14.0481.0QFN
144.0 x 4.018.0 x 18.0641.0QFN
155.0 x 5.018.0 x 18.0641.0QFN
164.0 x 4.010.0 x10.0721.0QFN
175.0 x 5.020.0 x 20.0721.0QFN
184.0 x 4.020.0 x 20.0801.0QFN
195.0 x 5.020.0 x 20.0801.0QFN
204.0 x 4.025.0 x 25.0881.0QFN
215.0 x 5.025.0 x 25.0881.0QFN
224.0 x 4.028.0 x 28.01001.0QFN
235.0 x 5.028.0 x 28.01001.0QFN

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