C2S

ChipIN Centre Instruction Enhancement Programme (IEPs) - Session 3

#	MATERIALS
1	Theoretical - Floor Planning
2	Theoretical - Import Design
3	Theoretical - Initial Chip Planning
4	Theoretical - Logic Synthesis
5	Theoretical - Power Planning
6	Theoretical - Timing Constraints
7	Theoretical - Understanding SCL PDK
8	Practical - Clock Tree Synthesis hands-on
9	Practical - Floor Planning hands-on
10	Practical - Placement hands-on
11	Practical - Power Planning hands-on
12	Practical - Routing hands-on
13	Practical - Synthesis hands-on