Ministry of Electronics and Information Technology
(MeitY)

Technical (Online) Session on "DIR-V VEGA Microprocessor based SoC design"

The Session will cover the following topic's:

• Overview of fundamental concepts of RISC-V Instruction Set Architecture (ISA).
• Various processor variants available within the RISC-V ecosystem, along with the range of peripheral IPs typically integrated into SoC designs, Insights into the typical architecture of VEGA-based SoCs and their integration methodology.
• Design and verification processes followed for VEGA SoCs, including validation strategies and methodologies to ensure reliable and robust SoC development.

Three Days Technical (Online) Session on Open-Source RISCV based SHAKTI Processor - Reg. Day 1

The Session will cover the following topic's:

• Introduction to FPGA
• FPGA Design flow
• Overview of SHAKTI Processor
• SHAKTI FPGA flow and demonstration
• SHAKTI Processor recap

Three Days Technical (Online) Session on Open-Source RISCV based SHAKTI Processor - Reg. Day 2

The Session will cover the following topic's:

• Introduction to SHAKTI SDK.

Three Days Technical (Online) Session on Open-Source RISCV based SHAKTI Processor Reg. Day 3

The Session will cover the following topic's:

• SHAKTI FPGA IP porting
• SHAKTI Linux porting

Technical session on SCL 180nm PDK

This technical session, will cover introduction to SCL PDK, Overview of Standard cells and IO cells from SCL used in Digital design., technical details and usage of Tech, LIB, and LEF files for standard and IO cells in the PDK within the digital design flow, technical details about map files, their usage, and importance, Physical verification (DRC, Antenna, LVS, PeX, etc.) with SCL PDK, Comprehensive overview of the Digital design flow with SCL PDK, Tapeout requirements for a Digital design with SCL PDK etc.

Technical Sessions by SCL on ASIC Design (Analog and Mixed Signal), Packaging & Testing related design issues, and SCL Foundry Process - Day 1

The Session will cover Analog and Mixed Signal ASIC Design Flow with SCL 180nm PDK and Packaging & Testing related design issues

Technical Sessions by SCL on ASIC Design (Analog and Mixed Signal), Packaging & Testing related design issues, and SCL Foundry Process - Day 2

The Session will cover SCL Foundry Process Features and Capabilities

Technical (Online) Session on SCL's 180nm technology process (both 4-metal and 6-metal) by SCL Chandigarh

The Session would cover the following topics:

• 1.8V, 3.3V, or 5V core CMOS
• 1.8V or 3.3V I/O library cells
• Single Poly and 4 to 6 metal layers
• High VT MOSFETs
• Deep N-well (isolated p-wells) for noise isolation
• Metal-Insulator-Metal (MIM) capacitors
• High-resistivity polysilicon resistors
• Selective cobalt salicidation
• Ti/TiN/AlCu/Ti/TiN metal interconnects
• 1.8V standard cells for logic design

Online Session on SCL 180nm Tapeout Process (November Shuttle) by SCL Chandigarh

The Session willl discuss the process for filling out the "Silicon Number Generation Form" Understanding the all columns of the "Silicon Numbering Table" Completing all sections of "Process Information Sheet" for SCL 180nm, Detailed guidance on the tapeout submission form, including: General Guidelines for filling out the form, Layout Grid options, Instructions for "Process details" section, tapeout checklist, Reports to be included with design submissions tapeout and packaging guidelines.

Technical (Online) Session on SCL's 180nm foundry requirements with an example/sample design for the tapeout

1. Grid size 0.005um settings
2. Powering the IC for IO and Core
3. Silicon Number with PCI insertion in the design
4. Layer revision block placement in the design
5. Seal-ring placement with GND connection
6. Dummy Fill with header
7. Pads connection till top metal (TOP_M)
8. Final Chip Origin placement at (0,0) after seal ring insertion
9. Making DRC clean
10. Making Antenna DRC clean
11. Generation of Devices type (or legal devices) used in layout report
12. Generation of List of all legal layers used before silicon number insertion in Excel Format (Layer Name + layer number + datatype)

Technical (Online) Session on SCL's Chip-on-Board (CoB) packaging options offered for C2S participating institutions targeting SCL 180nm

The session would cover the following CoB packaging details:

• CoB DIP Type
• CoB QFN/Leadless Type
• CoB PGA Type
• CoB Package (CoB DIP+QFN+PGA) parasitic (RC or RLC) details (Package Parasitic models, including example design simulations with package parasitics, etc.)
• CoB Package (CoB DIP+QFN+PGA) options bonding diagram creation/process flow details

Technical (Online) Session on SCL 180nm 4-metal and 6-metal processes by SCL Chandigarh

The session covers the following topics:

• Capabilities of SCLs 4-metal process
• Capabilities of SCLs 6-metal process
• Guidelines for selecting between the 4-metal and 6-metal processes based on design complexity and application
• Challenges associated with the 6-metal fabrication process

Technical (Online) Session on Creating Bonding Diagrams by SCL Chandigarh

The Session will deliver technical talk on Creating Bonding Diagrams and filling up the I/O pad information.

Online technical session by SCL team regarding the revised packaging options offered for C2S Institutions

The Session would cover SCL's 180nm foundry revised CoB packaging option details, including the following topics:

• Revised CoB QFN/PGA/DIP Types
• CoB Package (CoB DIP+QFN+PGA) parasitic impact due to bigger size (RC or RLC) details for the revised options (Package Parasitic models, including example design simulations with package parasitics, etc.)
• CoB Package (CoB DIP+QFN+PGA) options bonding diagram creation/process flow by SCL
• Brief background details on Revised Packaging Options

Online Session on extraction of layers for the Die GDS package bonding by SCL Team - Reg

The Session will cover Extraction of layers for the Die GDS package bonding

Online Technical Session on "2-Metal and 3-Metal Layer Process PDK" by SCL Team

The Session will cover the following topics:

• Introduction to SCL's 2-Metal/3-Metal SCL PDK in detail.
• Q & A Session

Technical (Online) Session on "Testing of Chip on Board (CoB) Packaged Devices" by SCL Team

This Session would cover Testing of Chip on Board (CoB) Packaged Devices in detail.

• Architecture of Questa
• Design and Verification Language Support
• Understanding GUI Features
• Questa Modes
• Debugging with the Schematic Window
• Debugging with the Dataflow Window
• Waveform Comparison
• Code Coverage
• Demo on Questa Prime

• Questa Lint
• Questa AutoCheck

• Questa CoverCheck
• Questa CDC

• SupportNet Login Process
• Overview of the SupportNet web-portal
• Downloading Binaries - flow
• Overview of On-Demand Trainings (ODTs) on Siemens EDA Tools
• Registration Process for ODTs
• Accessing ODTs
• Service requests through SupportNet web-portal

• Schematic entry and Spectre Analysis
• Custom Layout Design, Verification and Post-Layout Analysis
• Virtuoso Initial Setup, Schematic Design, Pre-Layout Simulation Setup Using ADE Explorer and Assembler, Running Simulations, etc. (will be covered by Cadence Team)
• Dummy Transistors, Shielding, Latch-Up, Guard Ring, PCell Design for MOS & Passive Devices, Layout XL Overview, Post-Layout Simulation, etc. (will be covered by Cadence Team)

• ASIC flow overview, Significance of Synopsys tools in the entire flow, RTL design example - Synchronous and Asynchronous FIFO
• FIFO RTL coding, FIFO Functional verification using Verilog
• Lint and CDC, UPF implementation, Synthesis, Gate level simulation
• Introduction to HVL based TB, Develop SV and UVM TB for Asynchronous FIFO, Develop test cases
• Asynchronous FIFO, Develop test cases, Develop other TB components, Coverage analysis, Verdi tool debug

• Introduction to Big Data and SeaScape Platform, setting up RedHawk-SC and performing basic EM/IR Analysis and various methods for checking IR Power drops
• Hands-on lab session on RedHawk-SC

• FAQs about latest SCL PDK

• Introduction to DFT, Types of Test and fault models Basic Scan Test Scan Insertion Flow, ATPG Flow ATPG Demo, Introduction to Compression

• Installing the Keysight EDA tools, accessing centrally hosted EDA licenses, setting up environment variables, support related, etc.

• The Session will cover some of the sources of power- and energy-inefficiency in today's microprocessors. etc.

• RTL Coding guidelines
• Async. FIFO Design and Simulation using Xcellium Tool

• Linting Using Candence Jasper Gold

• Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) using Cadence Jasper Gold

• X - Propagation using Cadence Jasper Gold

Introduction to Calibre EDA Tool, DRC Setup and Rule Violations check etc.

Technical (Online) Session on Keysight Cliosoft Software (Design Data Management tool)

Importance of Design Data Management (DDM), Introduction to Cliosoft's revolutionary solutions, SOS's Simple Solutions to Big Problems, Data Security, Network Storage Optimization, Design and IP Reuse, Live Demo and Case Studies etc.

Technical (Online) session on SCL 180nm PDK and its integration into the design flow.

During this technical session, participants will have the opportunity to clarify their doubts and queries related to SCL PDK.

Technical (Online) Session on accessing and using Xilinx Alveo U 55C and VCK5000 Versal FPGA Boards.

Introduction to Xilinx Platforms, Intro to Vitis for Acceleration Platforms, Vitis Tool Flow, Vitis Design Analysis, Alveo U55C High Performance Compute Card, VCK5000 Versal Development Card etc.

Technical (Online) Session on Introduction to Keysight ADS and Schematic Software

Introductory session on Keysight ADS and Schematic EDA Software.

Technical (Online) Sessions on Synthesis and Post Synthesis Flow by ChipIN Team

Writing/Defining timing constraints for Async. FIFO Design, TCL scripting for Synthesis, and Genus Synthesis Tool Flow

Technical (Online) Sessions on Synthesis and Post Synthesis Flow by ChipIN Team

Logic Equivalence Check, post synthesis simulations, zero delay simulation, unit delay simulation and sdf simulations using Xcelium Tool

Technical Session on Questa simulator and Linting - Day 1

Questa Sim Introduction (Features and Flows), Questa Sim usage in GUI, Command line and in-built examples demo, Questa Sim Advanced features discussion, Advanced GUI -Coverage, Debug etc.

Technical Session Questa simulator and Linting - Day 2

Introduction to Questa Design solutions and Introduction to Linting, Questa Lint, Methodologies and goals, Advanced Features, Demo and Graphical user interface, Queries etc.

Ansys Technical Session on Totem EDA Tool

The session will cover Totem Platform Overview, Totem Static Analysis, Totem Dynamic Analysis, Analysis, IP Model Creation, GUI Wizard etc.

Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 1

The Session Covers the Start of Physical Design: Import, Floorplan, IO fillers, and Power plan, creation of IO assignment file, MMMC file (GUI + Script) using Innovus Tool

Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 2

The session covers the Placement, Clock Tree Synthesis and STA: Placement, Creation of Clock tree spec file, CTS (Cluster, trial and full mode) and ECO to fix STA if any

Online Session on Installing the Latest Shared SCL PDK by ChipIN Team

During this technical session, participants will have the opportunity to clarify their doubts and queries related to SCL PDK installation.

Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 3

The session will cover the Routing, std. cell fillers and Sign-off, ECO post route and sign-off, Post Route netlist simulations, zero delay simulation, unit delay simulation, back annotation with sdf

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 1

The session will cover Custom Compiler Overview, Library Manager, Schematic Editor, Symbol Creation etc.

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 2

The session will cover PrimeWave Design Environment and Simulation etc.

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 3

The session will cover PrimeSim Continuum

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 4

The session will cover Layout Editor, SDL.

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 5

The session will cover Physical Verification and Parasitic Extraction

Technical (Online) session on SCL 180nm PDK

This technical session, will cover introduction to SCL PDK, Overview of Standard cells and IO cells from SCL used in Digital design., technical details and usage of Tech, LIB, and LEF files for standard and IO cells in the PDK within the digital design flow, technical details about map files, their usage, and importance, Physical verification (DRC, Antenna, LVS, PeX, etc.) with SCL PDK, Comprehensive overview of the Digital design flow with SCL PDK, Tapeout requirements for a Digital design with SCL PDK etc.

Technical (Online) Session on Keysight ADS HDS Software

Technical session on Keysight ADS HSD-High Speed Simulation: Signal Integrity, Power Integrity, Memory Design

Technical (Online) Session on Ansys PowerArtist EDA Tool

Introduction to PowerArtist, Steps to Power-Efficient RTL Design, Power Computation Fundamentals; PowerArtist Setup and Flow, RTL Import - "Elaborate", Perform Architectural Trade-Offs (Explore Power of Micro-Architectures); Static Power Efficiency Audit - "AnalyzeStaticEfficiency", Profile Real Application Scenarios (Vector Analysis and Power Profiling), Check Power versus Budget Early (Average and Time-Based Power Analysis), Visually Debug Power for Anomalies, Reduce Power using RTL Techniques etc.

Embedded for Beginners

Session Details [Click Here]

VLSI for Beginners

Session Details [Click Here]

Python for Beginners

Session Details [Click Here]

Introduction to MATLAB & Simulink

Session Details [Click Here]

Machine Learning using Python

Session Details [Click Here]

Online interactive session on EDA Tools installation

The session would be covering issues related to installing the Synopsys EDA tools, accessing centrally hosted EDA licenses, setting up environment variables, support related, etc.

MicroPython for Beginners

Session Details [Click Here]

Technical (Online) Session on Cadence Innovus EDA Tool

Introduction to Semi-Custom IC Design Flow (RTL-GDSII), Physical Design process and tool flow, Data interpretation for Physical Design, Physical design flow for Block and Chip level etc. Physical Implementation using Innovus that includes, Floor Planning, Power Planning, Placement, CTS, Routing, Timing and Power Analysis, Physical Verification etc.

Technical (Online) Session on Physical Design Tool flow - Day 1

The session will cover LEC check for synthesis netlist with post route netlist, Post Route netlist simulations, zero delay simulation, unit delay simulation, back annotation with sdf

Technical (Online) Session on Physical Design Tool flow - Day 2

The session will cover std. cells, io cells, fifo GDS-II stream in Virtuoso, silicon number insertion and seal-ring placement etc.

Online interactive session on Xilinx EDA Tools installation by CoreEL Team

The session would be covering overview of EDA Tools from AMD-Xilinx, Tool installation procedure, License acquisition procedure, frequently encountered issues, and solutions etc.

Technical (Online) Session on RTL to GDS Flow - Day 1

RTL to GDS Flow

Technical (Online) Session on RTL to GDS Flow - Day 2

RTL to GDS Flow

Technical (Online) Session on RTL to GDS Flow - Day 3

RTL to GDS Flow

Technical (Online) Session on RTL to GDS Flow - Day 4

RTL to GDS Flow

Technical (Online) Session on RTL to GDS Flow - Day 5

RTL to GDS Flow

Embedded for Beginners

Session Details [Click Here]

VLSI for Beginners

Session Details [Click Here]

Python for Beginners

Session Details [Click Here]

Introduction to MATLAB & Simulink

Session Details [Click Here]

MicroPython for Beginners

Session Details [Click Here]

RISC-V programming primer

-

Machine Learning using Python

Session Details [Click Here]

Data Analysis Using Python

Session Details [Click Here]

Technical Sessions by SCL on ASIC Design (Analog and Mixed Signal), Packaging & Testing related design issues, and SCL Foundry Process - Day 1

The Session will cover Analog and Mixed Signal ASIC Design Flow with SCL 180nm PDK and Packaging & Testing related design issues

Technical Sessions by SCL on ASIC Design (Analog and Mixed Signal), Packaging & Testing related design issues, and SCL Foundry Process - Day 2

The Session will cover SCL Foundry Process Features and Capabilities

Technical (Online) Session on Introduction to OpenPOWER by Dr. Hofstee (IBM)

This Session will cover OpenPower ISA, including its origins in the first RISC architecture, the history of the different variants of the architecture, and its current state as an open architecture managed by the OpenPOWER project under the Linux foundation. The discussion will include how the POWER compliancy subsets allow license-free implementations from very small processors that can be used in microcontrollers to the versions of the architecture used in the largest SMP systems.

Technical (Online) Session on OpenPower Microwatt microprocessor microarchitecture by Dr. Paul Mackerras (IBM)

The Session will cover OpenPower Microwatt microprocessor microarchitecture. This talk provides a general overview of Microwatt and gives an introduction to the microarchitecture of the Microwatt processor, including variants that support the integer and floating-point subsets of the architecture.

Technical Session on the registration process and MPW services offered by IMEC / EUROPRACTICE

The session will cover registration process and MPW services offered by IMEC / EUROPRACTICE

Technical (Online) Session on Keysight ADS RF Microwave EDA Tool

The Session will cover Power Amplifier Circuit Schematic design and simulation, Linear and Non-linear PA simulations, Impedance Matching tool, Smith Chart tool, Tuning and Optimization, Data Display, Parameter Sweeping, Design and Verification with Modulated Signals, Digital Pre-Distortion (DPD) Explorer etc.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx - Day 1

The session will cover Zynq-7000 architecture and Pynq Z2, Overview of the Zynq UltraScale+ MPSoC architecture, Identifying the key elements of the application processing unit (APU) and real-time processing, unit (RPU),various power domains and their control structure, Introduction to the Quick Emulator (QEMU), which is the tool used to run software for a device etc.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx - Day 2

Understanding how the PS and PL connect enables designers to create more efficient systems. Discussion on Peripherals on ZCU104 and Hands on Lab session etc.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx - Day 3

Introduction and need for HLS, Using Vitis HLS, Basic design flow of Vitis HLS and review generated outputs, Improving Performance, Optimizing Performance through Pipelining, Data Types etc.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx - Day 4

The session will cover Vitis Unified Software Platform Overview for Accelerator Development: Describes the elements of the development flow, such as software emulation, hardware emulation, and system run as well as debugging support for the host code and kernel code. Xilinx Runtime Library (XRT) Native APIs Describes the XRT native APIs used for opening a device, loading XCLBIN, creating buffers, executing a kernel, and controlling a graph etc.

Technical (Online) Session on Formal Verification by Synopsys Team - Day 1

The session will cover design qualification with VC Spyglass Lint & with VC Spyglass CDC followed by demonstration.

Technical (Online) Session on Formal Verification by Synopsys Team - Day 2

The session will cover dynamic HDL Simulations with VCS followed by demonstration.

Technical (Online) Session on Formal Verification by Synopsys Team - Day 3

The session will cover simulation debug with Verdi automated debug system followed by the demonstration

Online Interactive Session on Synopsys EDA Tools Installation by ChipIN Team

The session would be covering issues related to installing the Synopsys EDA tools, accessing centrally hosted EDA licenses, setting up environment variables, support related, etc.

Technical (Online) Session on Introduction to Power Amplifier design

The session will cover the Basics of Layout PA design in layout 3D view in layout & Introduction to RFPro, setting up EM simulation in RFPro, Advantages of RFPro over traditional emSetup, Generating test bench for EM circuit co-simulation etc.

Online Interactive Session on Implementing Unique Host-ID(s) for Effective EDA Tool Usage under C2S Programme

The session would be covering the procedure for changing the hostname of the EDA linux server, host-ID format and FAQ's related to unique Host-ID(s) implementation etc.

Technical (Online) Session on SCL's 180nm technology process (both 4-metal and 6-metal) by SCL Chandigarh

The Session would cover the following topics:

• 1.8V, 3.3V, or 5V core CMOS
• 1.8V or 3.3V I/O library cells
• Single Poly and 4 to 6 metal layers
• High VT MOSFETs
• Deep N-well (isolated p-wells) for noise isolation
• Metal-Insulator-Metal (MIM) capacitors
• High-resistivity polysilicon resistors
• Selective cobalt salicidation
• Ti/TiN/AlCu/Ti/TiN metal interconnects
• 1.8V standard cells for logic design

Technical (Online) Session on RTL to GDS Flow by using Cadence EDA Tool- Day 1

Introduction to IC Physical Design Flow, Cadence EDA tools for PD Flow, Functional Simulation using Incisive&Xcelium tool, Coverage analysis using IMC tool, RTL Synthesis using Genus Synthesis Solution, Synthesis Optimization for Power&Performance&Area, Logic Equivalence check using Conformal tool

Technical (Online) Session on RTL to GDS Flow by using Cadence EDA Tool- Day 2

Physical Implementation using Innovus that includes, Floor Planning, Power Planning, Placement, CTS, Routing, Timing Analysis using TEMPUS tool,Power Analysis VOLTUS tool, Parasitic Extraction,Generation of GDSII

Technical (Online) Session on Virtual SMART Lab

The Session will cover SMARTLAB usage - VLSI & Embedded domain.

Technical (Online) session Physical Design by ChipIN Team

The session will cover the block level DRC, Dummy Fill, Chip level DRC, Antenna DRC and LVS etc.

Technical (Online) session Physical Design by ChipIN Team

The Session will cover Timing check with Tempus, using sdf generated from Innovus as well as from Virtuoso etc

Technical (Online) session Physical Design by ChipIN Team

The session will cover Pex extraction and Spice simulations using spectre&unisim and tapeout to SCL foundry

Building 64-bit Microwatt OpenPOWER processor targeting Arty A7-100T FPGA Development Board

During this presentation, a step-by-step walkthrough will be conducted to demonstrate how a full system can be built based on the open and free 64-bit OpenPOWER ISA "Microwatt" processor, targeting the Arty A7-100T FPGA development board. Although Microwatt can be used as a microcontroller due to its small size, it is powerful enough to run Linux.

For this walkthrough, compute infrastructure at C-DAC will be leveraged to create the FPGA configuration bitfile. However, a full set of instructions will also be provided to perform the build, starting from a basic installation of Ubuntu 22.04.4.

The PowerPC architecture and the microarchitecture of the Microwatt processor were covered in previous sessions and will be briefly summarized. Additional background on the SoC architecture and the various tools used to build the Microwatt-based system will also be provided during the walkthrough.

Technical (Online) Session on Introduction to Chiplet design using Keysight ADS Software

Introduction to Chiplet
Benefits of Chiplet
Analyze Signal Integrity for Chiplet using UCIe standards
Use ADS and perform Die2Die simulation as per UCIe standards
Pre and Post layout Chiplet simulation in ADS

Online Session on SCL 180nm Tapeout Process (November Shuttle) by SCL Chandigarh

The Session willl discuss the process for filling out the "Silicon Number Generation Form" Understanding the all columns of the "Silicon Numbering Table" Completing all sections of "Process Information Sheet" for SCL 180nm, Detailed guidance on the tapeout submission form, including: General Guidelines for filling out the form, Layout Grid options, Instructions for "Process details" section, tapeout checklist, Reports to be included with design submissions tapeout and packaging guidelines

MicroPython for Beginners

Session Details [Click Here]

RISC-V programming primer

Will be announced

Embedded for Beginners

Session Details [Click Here]

VLSI for Beginners

Session Details [Click Here]

Python for Beginners

Session Details [Click Here]

Introduction to MATLAB & Simulink

Session Details [Click Here]

Technical (Online) Session on ADS QuantumPro by Keysight

The session will cover the Quantum Technology: An Overview, Quantum EDA at Keysight, Designing for Superconducting Qubits in ADS, QuantumPro, Designing for Basic Quantum Amplifiers

Technical (Online) session on Ansys EDA Tool

Introduction to the Power Analysis concepts, need of RTL power at early stage and inputs required for an RTL power analysis. It covers how PowerArtist Analyzes the RTL for average power, Introduction to PowerArtist GUI, interactive power debug feature using GUI.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool - Day 1

Installation of Xilinx EDA Tools, Overview of Xilinx FPGA architectures, FPGA and SoC boards, Vivado tool flow: Design entry, Simulation, Synthesis, Implementation and Programming, Introduction to IP Integrator and IP based Design etc.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool - Day 2

Overview of Zynq-7000 and Zynq UltraScale+ MPSoC architectures, Vitis tool flow: Exporting hardware, platform and application project creation, Adding Peripherals and writing applications to access added peripherals, Working with DMA and Interrupts, Creating a Boot image etc.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool - Day 3

Overview of Vitis HLS design flow, Basic design flow of Vitis HLS and review of generated outputs, Improving area and resource utilization, Creating a processor system using the IP created from HLS etc.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool - Day 4

Introduction to Xilinx Platforms, Vitis for Acceleration Platforms and Vitis Design Analysis

• Vitis Unified Software Platform Overview for Accelerator Development
• Xilinx Alveo U55C and VCK5000 Versal FPGA Boards
• Creating Vitis Project on both AI Engines and the Adaptable Engine using Vector Add

Technical (Online) Session on MPW Services and Other technical topics related to PDKs supported by M/s. IMEC

MPW Services and Other technical topics related to PDKs supported by M/s. IMEC

Technical (Online) Session on SCL's 180nm foundry requirements with an example/sample design for the tapeout

1. Grid size 0.005um settings
2. Powering the IC for IO and Core
3. Silicon Number with PCI insertion in the design
4. Layer revision block placement in the design
5. Seal-ring placement with GND connection
6. Dummy Fill with header
7. Pads connection till top metal (TOP_M)
8. Final Chip Origin placement at (0,0) after seal ring insertion
9. Making DRC clean
10. Making Antenna DRC clean
11. Generation of Devices type (or legal devices) used in layout report
12. Generation of List of all legal layers used before silicon number insertion in Excel Format (Layer Name + layer number + datatype)

Technnical (online) Session on System-level Simulation for RADAR/5G/Phased Array/SATCOM Applications

System-level Simulation for RADAR/5G/Phased Array/SATCOM Applications

Technical (Online) Session on TCAD by Synopsys Team

Day 1: Introduction to Technology Computer Aided Design (TCAD), Creating, Editing and Running Sentaurus Workbench projects, Visualizing TCAD simulation results using Sentaurus Visual etc.

Technical (Online) Session on TCAD by Synopsys Team

Day 2: Building a simple NMOS device from scratch in Sentaurus Process for device simulations, Overview of FinFET based CMOS inverter's process flow in Sentaurus Process Explorer, etc.

Technical (Online) Session on TCAD by Synopsys Team

Day 3: Simulating DC transfer and output characteristics of a MOSFET, Simulating AC characteristics of a MOSFET etc.

Technical (Online) Session on Ansys Totem - Getting Started with Mixed-Signal (AMS) IP and SoC Power Integrity and Reliability Signoff

The Session will cover electromigration Multiphysics sign-off solution for transistor-level and mixed-signal designs.

Technical (Online) session on Ansys EDA Tool

The Session would cover the following topics:

• Introduction to the Power reduction concepts for various categories like memory, clock, and data paths
• Need of RTL power reduction at early stage
• Inputs required for RTL power reduction analysis
• PowerArtist GUI for reduction
• Interactive power debug along with live demo
• Introduction to Ansys PowerArtist advanced features like vector scoring, power and quality metrics tracking, RTL power models for Power Grid Integrity and thermal integrity
• Improved RTL power accuracy using Timing Aware, Physical Aware, Advanced delay aware glitch, and emulator flows

Technical (Online) Session on SCL's Chip-on-Board (CoB) packaging options offered for C2S participating institutions targeting SCL 180nm

The session would cover the following CoB packaging details:

• CoB DIP Type
• CoB QFN/Leadless Type
• CoB PGA Type
• CoB Package (CoB DIP+QFN+PGA) parasitic (RC or RLC) details (Package Parasitic models, including example design simulations with package parasitics, etc.)
• CoB Package (CoB DIP+QFN+PGA) options bonding diagram creation/process flow details

Technical (Online) Session on SMART LAB by NIELIT Calicut

The session aims to drive the advancement of VLSI and Embedded Systems design, fostering research and innovation in electronics development across the nation

Technical (Online) Session on Timing and Power Signoff using Cadence EDA Tools by Entuple Team

Session-1: (Time: 10:00 AM to 11:30 AM)

• Introduction to Static Timing Analysis using TEMPUS tool
• Understand how to setup and run
• Report and analyze Static Timing results
• Timing path analysis and reports

• Timing Debug and Tempus ECO Flow
• Run Tempus ECO analysis
• Timing closure with Tempus
• Sign-off using Innovus

• Introduction to Low Power IC Design
• Power Analysis using Innovus
• Voltus IC Power Integrity Solution Overview
• Basic flow using VOLTUS tool

• Early Rail Analysis
• Power-Grid View Library Generation
• Static & Dynamic Power Analysis and IR Rail Analyses
• Power Sign-off using Innovus

Technical (Online) Workshop on the Veloce Emulator Platform by Siemens for institutions participating under C2S Programme (100+ academic institutions) and for start-ups/MSMEs (35+ Start-ups) under the DLI Programme

The workshop will cover the following topics:

• Introduction to Veloce Hardware platform.
• Design Compilation Flow
• Runtime Flow
• Debug flows
• Introduction to Transactors and its integration.
• Brief Intro to Veloce Apps

Technical (Online) Session on Introduction to the Registration Process and MPW Services Offered by M/s. MUSE Semiconductor for institutions participating under C2S Programme (100+ academic institutions) and for start-ups/MSMEs (35+ Start-ups) under the DLI Programme

Introduction to the Registration Process and MPW Services offered by MUSE Semiconductor. The session outlines detailed guidelines and procedures for academia, start-ups, and MSMEs to access the MPW services offered by MUSE Semiconductor.

Technical (Online) Session on MPW Services and Comprehensive support offered by M/s. IMEC

ASIC Packaging

Technical (Online) Session on Adding Custom Instructions to MicroWatt OpenPOWER Processor by Dr. H. Peter Hofstee (IBM)

This session will provide a comprehensive overview of how to add custom instructions to the MicroWatt OpenPOWER processor while maintaining ISA compliance. Using a simple spiking neural network as an example, the required changes to the design files will be demonstrated. The session will also cover testing and using the new instructions through inline assembly commands in a C program.

Technical (Online) Session on Open-Source RISCV based Shakthi Processor

The session covers the following topics:

• Overview of Shakthi Processor
• FPGA implementation of Shakthi processor
• Synthesis and Verification framework
• Introduction to integrating a user IP
• Shakthi SDK

Technical (Online) Session on Cellular, 5G, Satcom and NTN using SystemVue by M/S Keysight

Abstract of the session: The rapid evolution of communication technologies necessitates advanced tools for designing and simulating complex systems. PathWave System Design (SystemVue) emerges as a comprehensive solution, enabling efficient development and validation of cellular, 5G, satellite, and Non-Terrestrial Network (NTN) designs. This paper explores the capabilities of SystemVue in addressing the unique challenges of these domains. For cellular and 5G applications, SystemVue offers robust simulation libraries, including 5G New Radio (NR) components compliant with 3GPP standards, facilitating accurate modeling of modulation schemes and transceiver elements. In satellite communications, SystemVue supports DVB-S2X standards, providing detailed channel models and signal analysis tools essential for optimizing link performance under varying conditions. Additionally, the tool's NTN features enable precise trajectory visualization and end-to-end physical layer simulations, crucial for the deployment of next-generation networks. A key highlight is the integration of phased array beamforming technology, which enhances signal directionality and strength, crucial for both terrestrial and non-terrestrial applications. By integrating seamlessly with other Keysight tools, SystemVue ensures a holistic approach to virtual prototyping, significantly reducing the time and cost associated with physical testing. This session highlights the strategic advantages of leveraging SystemVue for the design and simulation of cutting-edge communication systems.

A Preliminary Getting Started Online Session by Silvaco on 18th December 2024

The session may cover the following topics (Agenda): EDA Tools offered by Silvaco for C2S & DLI Programmes Platform requirements, including software and hardware (Compute Infra) to support Silvaco EDA Tools. Tools installation and accessing centrally hosted licenses. Setting up environment variables and invoking the Tools. Support-related aspects and other relevant topics.

Technical (Online) Session Titled "Open Revolution in ASIC Design: OpenROAD and OpenPOWER Microwatt"

The semiconductor industry is undergoing a transformative shift with the rise of open-source initiatives in ASIC design. This presentation explores the Open Revolution led by two groundbreaking projects: OpenROAD and OpenPOWER Microwatt. OpenROAD democratizes chip design with a fully automated, RTL-to-GDSII workflow, eliminating traditional cost and complexity barriers. Complementing this, OpenPOWER Microwatt offers an open-source, lightweight implementation of IBM's POWER ISA, enabling customization, experimentation, and scalability. Together, these platforms empower innovators, startups, and academia, fostering unprecedented accessibility and innovation in custom silicon design.

Technical Session on System Designer for PCIe using Keysight ADS

The session may cover the following topics (Agenda):
PCIe Introduction Challenges for PCIe Simulation ADS PCIe simulator Seasim Interface PCIe Compliance Tests PCIe AMI model builder.

Awareness Session on Intellectual Property Rights (IPR) for C2S Participating Institutes

Technical (Online) Awareness Session on Intellectual Property Rights (IPR) for C2S Participating Institutions

Technical (Online) Session on Device Modelling Solution by Keysight

This session will provide a general overview of Keysight Device Modeling tools for semiconductor devices: The Integrated Circuit Characterization and Analysis Program (IC-CAP).

Device Modeling IC-CAP software is the industry standard for semiconductor device modeling and characterization. It extracts accurate compact models for high speed/digital, analog, power electronics, and power RF applications. It enables foundries and integrated device manufacturers (IDMs) to streamline semiconductor device modeling workflows for silicon CMOS, Bipolar, compound gallium arsenide (GaAs), gallium nitride (GaN) and many other IC devices of the following key features:

Open device modeling software architecture enhances accuracy and flexibility to create and automate measurement, extraction and verification procedures. Turnkey extraction solutions for industry standard CMOS models, such as BSIM3/BSIM4, PSP and HiSIM,. minimize the learning curve and maximize model accuracy. Direct links to major commercial simulators ensure consistency between extracted models and the simulators used by circuit designers.

Technical Session on Getting Started with Ansys Totem EDA Tool

Introduction to Totem AMS platform Static Power Integrity EMIR Analysis Environment variables to setup and run Totem Totem GUI Totem Text Reports Totem Results Overview and Debug Introduction to Dynamic EMIR Analysis

Technical (Online) Session on SCL 180nm 4-metal and 6-metal processes by SCL Chandigarh

The session covers the following topics:

• Capabilities of SCLs 4-metal process
• Capabilities of SCLs 6-metal process
• Guidelines for selecting between the 4-metal and 6-metal processes based on design complexity and application
• Challenges associated with the 6-metal fabrication process

Technical (Online) Session on UTMOST4, Gateway, SmartSpice & Expert EDA Tool by M/s Silvaco

The session covers the following topics:

• UTMOST4
• Gateway and SmartSpeice
• Expert

Four-day Online Technical Training Session on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx

Day 1 :

• Vitis Tool Flow: Introduction to the Vitis Unified Software Platform: Explains how software/hardware engineers and application developers can benefit from the Vitis unified software environment and OpenCL framework
• Vitis Unified Software Platform Overview for Accelerator Development: Describes the elements of the development flow, such as software emulation, hardware emulation, and system run as well as debugging support for the host code and kernel code

Four-day Online Technical Training Session on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx

Day 2 :

• Introduction to Hardware Acceleration: Outlines the fundamental aspects of FPGAs, SoCs, and ACAPs that are required to guide the Vitis tool to the best computational architecture for any algorithm
• Vitis Execution Model and XRT: Describes the XRT and the OpenCL APIs used for setting up the platform, executing the target device, and post-processing
• Xilinx Runtime Library (XRT) Native APIs: Describes the XRT native APIs used for opening a device, loading XCLBIN, creating buffers, executing a kernel, and controlling a graph

Four-day Online Technical Training Session on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx

Day 3 :

• Design Analysis: Profiling: Describes the different reports generated by the tool and how to view the reports that help to optimize data transfer and kernel optimization using the Vitis analyzer tool
• Debugging: Explains the support for debugging host code and kernel code as well as tips to debug the system
• Kernel Development: Introduction to C/C++ based Kernels, Describes the trade-offs between C/C++, OpenCL, and RTL applications and the benefits of C-based kernels

Four-day Online Technical Training Session on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx

Day 4 :

• Kernel Development: Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators: Describes how the Vitis unified software development provides RTL kernel developers with a framework to integrate their hardware functions into an application running on a host PC connected to an FPGA via a PCIe® interface
• Optimizing the Performance of the Design: Illustrates various optimization techniques, such as optimizing the host code and data transfer between kernels and global memory, to improve kernel performance

IEP on ASIC Analog Design Using 180nm PDK (Hybrid)

Insights into Schematic-to-GDSII using Cadence and Siemens EDA Tools for Analog IC design with a focus on 180nm PDK

Technical (Online) Session on Silvaco EDA UTMOST4, Gateway and SmartSpice & Expert

The session may cover the following topics (Agenda):

• UTMOST4- SPICE Model Extraction (10:00 am - 10:45 am)
• Gateway - Schematic Editor and SmartSpice - Simulator (10:45 am - 11:30 am)
• Expert - Layout Editor and Smart DRC/LVS (11:30 am - 13:00 pm)

Technical Online Session on Design For Test(DFT) flow using Modus

• Session-1: (10 am - 11:30 am)
  • Introduction to DFT (Design for Test)
  • Basic Purpose and Target of Testing
  • DFT design rules
• Session-2: (11:45 am - 1:15 pm)
  • DFT-based RTL Synthesis using Genus tool
  • Basic Diagnostic capabilities
  • ATPG Based DFT flow on Modus
• Session-3: (2 pm - 3:30 pm)
  • Build fault model and test modes
  • Verify test structures
  • Automatic Test Pattern Generation (ATPG)
• Session-4: (3:45 pm - 5:15 pm)
  • ATPG Analysis using Modus tool
  • Create static tests
  • Write vectors

Technical (Online) Training Session on Ansys RedHawk-SC Quick Start- Part 1

The session covers the following topics:

• Big Data and SeaScape Platform
• Setting up RedHawk-SC and performing basic EM/IR Analysis
• Introduction to SeaScape APIs and MapReduce
• Key features include:
• Checking IR drops on power grids
• Calculating power
• Introduction to static and dynamic IR analysis

Two-Days Technical (Online) Session on RTL Design and Simulation using VCS and Verdi Synopsys EDA Tool by Synopsys Team - Day 1

The session details are as follows:

Two-Days Technical (Online) Session on RTL Design and Simulation using VCS and Verdi Synopsys EDA Tool by Synopsys Team - Day 2

The session details are as follows:

Technical (Online) Session on Ansys HFSS EDA Tool - Day 1

The session details are as follows:

Technical (Online) Session on Ansys HFSS EDA Tool - Day 2

The session details are as follows:

Technical (Online) Session on Creating Bonding Diagrams by SCL Chandigarh

The Session will deliver technical talk on Creating Bonding Diagrams and filling up the I/O pad information.

Technical Online Session on Formal Verification using JasperGold

The session details are as follows:

Technical (Online) Session on Chiplet-Based Designs with EDA: Shaping the Future of Semiconductor Packaging

The session details are as follows:

• Introduction to Chiplet
• Advantages of Chiplet over traditional flow
• Analyze Signal Integrity for Chiplet using UCIe standards & BoW standards
• Use ADS and perform Die2Die simulation as per UCIe & BoW standards
• Pre and Post layout Chiplet simulation in ADS
• Calculate VTF Loss and crosstalk

Technical (Online) session on SMART LAB by NIELIT Calicut

SMART Lab Demonstration (VLSI/Embedded): Session covering smartlab usage - VLSI & Embedded domain.

Technical (Online) Session on Silvaco EDA UTMOST4, Gateway and SmartSpice & Expert

The session details are as follows:

• UTMOST4 - SPICE Model Extraction (10:00 am - 10:45 am)
• Gateway - Schematic Editor and SmartSpice - Simulator (10:45 am - 11:30 am)
• Expert - Layout Editor and Smart DRC/LVS (11:30 am - 13:00 pm)

Two-Days Workshop on Questa Static Formal verification solutions by CoreEL Team - Day 1

The session details are as follows:

• Introduction to FPGA tool flow
• Position of Siemens EDA Formal tools in FPGA tool flow
• Need for Early Verification
• Formal Adaptation
• Overview of Questa Formal tools
• Intro to Questa Lint
• Lint Workflow
• Why is Lint Necessary?
  • Checks
  • Methodology and Goals
• Questa Result Analysis
• Tool Demonstration
• Intro to Questa Autocheck
  • Autocheck Workflow
  • Predefined Checks for Common Problems
  • Autocheck Benefits
  • Autocheck Status Flow
• Questa results Analysis
• Tool Demonstration
• Intro to Questa Covercheck
  • Workflow
  • CoverCheck Benefits
  • Checks for Coverage Exclusions
  • Questa CoverCheck with QuestaSim
• Tool Demonstration
• Intro to Questa CDC
  • CDC Workflow
  • Need for CDC Verification
  • Common CDC Issues
  • Analysis and Debugging
• Tool Demonstration

Two-Days Workshop on Questa Static Formal verification solutions by CoreEL Team - Day 2

The session details are as follows:

• Intro to Questa PropCheck
• PropCheck Workflow
  • Property Checking Methodology
  • Common Use Cases
  • Result Analysis
• Tool Demonstration
• Intro to X-Check
• X-Propagation Challenges
• X-Check Methodology
• Debugging Techniques
• Tool Demonstration
• Intro to Questa Equivalent Check
• Equivalence Checking Workflow
  • Functional and Structural Comparisons
  • Debugging and Result Analysis
• Tool Demonstration

Online Session on Keysight ADS and SystemVue Software Installation, License Access, Environment Setup & Support related issues

The Session would be covering Installation of Keysight ADS and SystemVue software, accessing licenses, setting up environment variables & support related issues.

Technical (Online) Session on Automating Digital Implementation with Cadence: Foundational Flow & Stylus CUI - Day 1

The session details are as follows:
Session 1: Introduction to Foundational Flow

• Overview of Digital Implementation Flow
• Introduction to Flat, Hierarchical, and ILM Flows
• Basic Project Setup:
  • Technology Files
  • Libraries
  • Constraints
• Hands-on: Running Flat Design Flow

• Understanding Hierarchical Design
• ILM Flow:
  • Purpose
  • Generation
  • Usage
• Setting up a Hierarchical Flow
• Hands-on: Creating and Using ILM Models

Technical (Online) Session on Automating Digital Implementation with Cadence: Foundational Flow & Stylus CUI - Day 2

Session 3: Stylus CUI and Customization

• Introduction to Stylus Common User Interface (CUI)
• Differences Between Traditional and Stylus CUI
• Setting up a Stylus Environment
• Hands-on: Running Stylus CUI-based Flow

• Comparative Analysis of Flat, Hierarchical, and Stylus CUI Flows
• TCL Scripting and Automation
• Hands-on: Customization and Execution of Demo design with ASAP 7nm
• Q&A and Concluding Remarks

Technical (Online) Session on Silvaco EDA UTMOST4, Gateway, SmartSpice and Expert EDA Tools by M/s Silvaco

The session details are as follows:

• UTMOST4 - SPICE Model Extraction
• Gateway - Schematic Editor and SmartSpice - Simulator
• Expert - Layout Editor and Smart DRC/LVS

Two-Days Technical (Online) Session on Ansys RedHawk-SC Software by M/s Ansys -Day 1

The session details are as follows:

• Introduction to Power Integrity and Reliability Signoff Analysis for Digital IP and SoCs, Introduction to Big Data, SeaScape Platform and RedHawk -SC, Lab Session on Setting up RedHawk-SC, Input Data Integrity Checks
• PG Grid Weakness Checks - Shorts, Missing Via Checks and Instance Disconnect Checks, PG Grid Robustness - Shortest Path Resistance (SPR) and Effective Resistance (Reff), Lab Session on Grid Weakness
• Q & A

Two-Days Technical (Online) Session on Ansys RedHawk-SC Software by M/s Ansys -Day 2

The session details are as follows:

• Power Calculation, Static Voltage Drop (IR) and DC/Avg Electromigration (EM) Analysis, Lab Session on Static IR/EM
• Dynamic Voltage Drop (DVD) Analysis and Peak/RMS EM Analysis Lab Session on DVD Analysis
• Q & A

Online technical session by SCL team regarding the revised packaging options offered for C2S Institutions

The Session would cover SCL's 180nm foundry revised CoB packaging option details, including the following topics:

• Revised CoB QFN/PGA/DIP Types
• CoB Package (CoB DIP+QFN+PGA) parasitic impact due to bigger size (RC or RLC) details for the revised options (Package Parasitic models, including example design simulations with package parasitics, etc.)
• CoB Package (CoB DIP+QFN+PGA) options bonding diagram creation/process flow by SCL
• Brief background details on Revised Packaging Options

Technical (Online) Session on "Photonics Designer in Keysight ADS"

The session details are as follows:

• Overview of Photonics - PDA Market, Design Flow Challenges
• Keysight Photonic Designer
• What's offered in Keysight's Photonics solution - Scope
• Brief about Photonics Example PDK in ADS
• Brief Demo of one/two examples (MRR, EOE, etc.)
• How our Solution is better compared to our Competitors
• Collaboration with Foundries for PDK availability for ADS

Technical (Online) Session on Design and Simulation of Electronic Circuits with PCB Implementation

The Session may cover the following topic's (Agenda):

1. Electronic Product Design Cycle
2. Design Entry (Schematic): Design Example - Hands On Working with projects and its configuration, Parts Manager, Add parts in parts manager, Search the parts - Global/Local Search Parts placements, Wiring your circuits: Auto/Manual/Virtual Wiring, Annotate your circuit, Property Editor: Parts/Pins/Nets
3. Predict the behavior of your circuit: Circuit Simulation - Hands On Setting up your circuit for simulation and netlist generation, Verify circuit parameters using Interactive waveform viewer, Measurement Functions, Types of Analysis, DC Bias Point Analysis : Bias point display, DC Analysis : DC Sweep, AC Analysis : AC Sweep, Transient/Time Domain Analysis, Parametric Sweep
4. Generate the BOM (Bill of Material)
5. Introduction to PCB and Layout Design Process: -Hands On Prepare your circuit for layout design,Package Mapping and netlist generation for Layout design, Design stackup and Layout configuration (Floor planning), Create board outline and Package Keep out area, Introduction to Industry Standards, Component Placement and Alignment, Placement techniques : Understand the, importance of parts placement in Layout, Auto Placement/Manual, Component Alignment, Define spacing constraint b/w component to component and component to obstacle Constraint Manager.

Four-Days Technical (Online) Session on Design Verification using Assertions in System Verilog by Synopsys Team - Day 1

Day 1: The session covers the following topics:

• Introduction of Dynamic Environment & Advantages, Data types, Types of Arrays, Operators, Mailbox, OOP- Encapsulation, Inheritance, Polymorphism etc.
• Q & A
• Lab Session: Hands on examples on operators, array methods, Hands on examples on OOP, APB Transaction, class definition, methods, constraints etc.

Four-Days Technical (Online) Session on Design Verification using Assertions in System Verilog by Synopsys Team - Day 2

Day 2: The session covers the following topics:

• Shallow copy & Deep copy, Constraints and Randomization, Functional coverage
• Q & A
• Lab Session on Declaration of different class properties & methods, Implementing constraints and randomization examples, Functional coverage etc.

Four-Days Technical (Online) Session on Design Verification using Assertions in System Verilog by Synopsys Team - Day 3

Day 3: The session covers the following topics:

• Introduction to assertions, Immediate and concurrent assertions, Reusable property declaration, Sequence operators, White box and black box assertions.
• Q & A
• Lab Session: Different patterns generation using constraints Examples for mailbox methods, Examples for static properties & methods

Four-Days Technical (Online) Session on Design Verification using Assertions in System Verilog by Synopsys Team - Day 4

Day 4: The session covers the following topics:

• Assertion based verification, Listing down assertions, Introduction to formal property verification.
• Q & A
• Lab Session: Assertion hands on examples, setting up assertion based verification environment for pattern detector.

Technical (Online) Session on Silvaco EDA UTMOST4, Gateway, SmartSpice & Expert EDA Tools by M/s Silvaco

The Session may cover the following topic's (Agenda):

• UTMOST4 - SPICE Model Extraction
• Gateway - Schematic Editor and SmartSpice - Simulator
• Expert - iPDK Flow

Interactive Online Session on Siemens Questa Sim EDA Tool

The Session may cover the following topic's (Agenda):

• Introduction to QuestaSim: Overview and Capabilities
• QuestaSim Setup and Configuration
• Graphical User Interface (GUI) Navigation
• Project Initialization and Configuration
• Compilation and Analysis of Design Files
• Simulation & Code Coverages
• Interactive Q&A

Technical (online) Session on Power Electronics Modeling, Design, and Simulation using Keysight ADS

The Session may cover the following topic's (Agenda):

• Introduction to Power Electronics design
• Use of WBG devices like SiC & GaN along with its challenges
• EM Simulation of PCB for parasitics extraction
• EM-circuit co-simulation
• Thermal analysis
• Radiation effect for SMPS based design

Two-Days Online Session on Mixed-Signal IC Design and Verification Using AoT and DoT Methodologies with Cadence EDA Tool - Day 1

The Session will cover the following topic's:

• Session 1: Introduction to Mixed-Signal Verification and Methodologies
  • Overview of Mixed-Signal IC Design and Verification
  • Challenges in Simulation and Testability
  • Introduction to AoT (Analog-on-Top) and DoT (Digital-on-Top) Methodologies
• Session 2: AoT Design Flow
  • Floorplan creation for the top level design in Virtuoso
  • Implement digital block in Innovus using the VDI interface
  • Creating Abstract for the Digital Block

Two-Days Online Session on Mixed-Signal IC Design and Verification Using AoT and DoT Methodologies with Cadence EDA Tool - Day 2

The Session will cover the following topic's:

• Session 3: DoT Design Flow
  • Design import and timing analysis in Innovus
  • Implementation of the AMS block in Virtuoso
  • Creating FTM of the AMS block and running top level STA
• Session 4: DoT Verification Flow
  • ECO, STA and PVS
  • Creating Abstract for the Digital Block
  • Q&A and Concluding Remarks

Online Interactive Session on EDA Essentials & Beyond: An Introduction to Cadence Resources and Networks

The Session will cover the following topic's:

• Introduction to Cadence Academic Network (CAN)
• Cadence Global Academic Collaborations
• Cadence Customer Education Offerings and ASK Portal Resources
• Q&A and Closing Remarks

Technical (Online) Session on Antenna Design and Integration with System using Keysight ADS

The Session will cover the following topic's:

• ADS Electro-Magnetic (EM) Simulations Overview
• Planar Antenna design and EM simulation in ADS
• Python Scripting to design Planar Antenna and Planar Array
• Integration of Planar Array with the RF Frontend Design

Technical (Online) Session on Silvaco EDA UTMOST4, Gateway, SmartSpice & Expert EDA Tools by M/s Silvaco

The Session will cover the following topic's:

• UTMOST4 - SPICE Model Extraction
• Gateway - Schematic Editor and SmartSpice - Simulator
• Expert - Layout Editor and Smart DRC/LVS

Three Days Technical (Online) Session on Open-Source RISCV based SHAKTI Processor - Reg. Day 1

The Session will cover the following topic's:

• Introduction to FPGA
• FPGA Design flow
• Overview of SHAKTI Processor
• SHAKTI FPGA flow and demonstration
• SHAKTI Processor recap

Three Days Technical (Online) Session on Open-Source RISCV based SHAKTI Processor - Reg. Day 2

The Session will cover the following topic's:

• Introduction to SHAKTI SDK.

Three Days Technical (Online) Session on Open-Source RISCV based SHAKTI Processor Reg. Day 3

The Session will cover the following topic's:

• SHAKTI FPGA IP porting
• SHAKTI Linux porting

Technical (Online) Session on Design Closure Techniques - STA and Timing Closure in Vivado - Day 1

The Session will cover the following topic's:

• Introduction to Static Timing Analysis
• Timing Paths - Reg to Reg path, Input to Reg path, Reg to Output paths
• Clock Variations and Uncertainties
• Static Timing Analysis - Setup and Hold check (Equations)
• Analyzing Timing Reports
• Introduction to AMD Design Constraints
• AMD Performance Baselining Flow for Timing Closure
• Lab1 : Baselining Flow : Apply clock constraints, IO Constraints
• Lab2 : Timing Constraints Wizard usage ( to apply clock constraints, IO constraints, virtual clock)

Technical (Online) Session on Design Closure Techniques - STA and Timing Closure in Vivado - Day 2

The Session will cover the following topic's:

• Multicycle Paths and False Paths /Timing Exceptions
• Lab1: Lab to demonstrate how to constrain Multicycle paths and False paths
• Synthesis Techniques: Pipelining, resource sharing and register duplication
• Lab2: Applying Pipelining for improving design performance
• Implementation Techniques: Incremental Compile, Physical Optimization and Floor planning
• Lab3: Incremental Compile for improving your design response time

Technical (Online) Session on Design Closure Techniques - STA and Timing Closure in Vivado - Day 3

The Session will cover the following topic's:

• Introduction to Floorplanning and Placement blocks (pblocks)
• Lab1: Floorplanning a complex design using pblocks
• Lab2: Understand the physical optimization technique for timing closure
• Clock groups and Clock Domain Crossing concepts
• Synchronization Techniques - Addressing Metastability issues using Single bit Metastability resolution circuits and Asynchronous FIFO
• Lab3: Clock Domain Crossing and Synchronization circuits (Report CDC and apply ASYNC_REG property in your design)

Technical (Online) Session on "DIR-V VEGA Microprocessor based SoC design"

The Session will cover the following topic's:

• Overview of fundamental concepts of RISC-V Instruction Set Architecture (ISA).
• Various processor variants available within the RISC-V ecosystem, along with the range of peripheral IPs typically integrated into SoC designs, Insights into the typical architecture of VEGA-based SoCs and their integration methodology.
• Design and verification processes followed for VEGA SoCs, including validation strategies and methodologies to ensure reliable and robust SoC development.

Technical (Online) Session on Open-source tools for improved debugging and modularity with Chisel by Dr. H. Peter Hofstee (IBM)

Abstract of the Talk: This Talk will introduce a set of open-source tools and a new standard for typed streams to deliver a better experience for designing with the Chisel high-level design language. Currently, while Chisel allows designs to be specified in a higher-level language, debugging a design still happens at a very low level. We introduce several new tools compatible with Chisel to address this.

• The Tywaves waveform viewer, built on the "surfer" waveform viewer platform, enables waveforms that preserve and properly visualize the Chisel data structures and types. The ChiselWatt OpenPOWER processor is used as an example design.
• We also introduce a tool (ChiselTrace) that allows for improved traceback from selected signals that can be used to more efficiently discover the causes of an erroneous signal value.
• Next, we introduce the Tydi framework, that provides typed streaming interfaces that can be used to improve modularity and reusability of designs in Chisel (Tydi-Chisel) as well as other languages. At the end we summarize on how this collection of tools can simplify hardware design, and we discuss how we plan to take this work forward.

Two- Days Technical (Online) Session on Low-Power RTL Synthesis Flow using Cadence EDA Tools

Day 1

Session-1: Joules Power Calculator (2:00 PM - 3:30 PM)

• Introduction to Cadence Joules RTL Power Solution
• Estimating the Power and Joules Power Reduction Techniques
• Genus-Joules Integration

Session-2: Low-Power Specification Format (3:45 PM - 5:30 PM)

• Low-power concepts and strategies
• Implement a power switch
• Debugging Design Scenarios

Two- Days Technical (Online) Session on Low-Power RTL Synthesis Flow using Cadence EDA Tools

Day 2

Session-3: Genus Low-Power Synthesis Flow (2:00 PM - 3:30 PM)

• Low-Power Synthesis Flow
• Power Reduction
• Low-Power Methodologies: MSV, PSO, and DVFS

Session-4: Low-Power Synthesis Flow with Genus Stylus (3:45 PM - 5:30 PM)

• Troubleshooting Low-Power Design
• Checking a Low-Power Design with Conformal Software
• Genus-Joules Integration

Online Session on extraction of layers for the Die GDS package bonding by SCL Team - Reg

Technical (Online) Session on Post-Silicon Validation, Characterization, Testing, and Packaging Services by Tessolve for C2S Participants

The Session will cover the following topics:

• Overview of Tessolve and Post Si Support Flow.
• Capabilities in Test Engineering
• Bench Characterization Capabilities
• Overview of Product Engineering
• Introduction to Qualification
• Expertise in PCB Engineering
• Capabilities in Packaging
• Q & A and support for C2S participants.

Smarter Semiconductor Validation to Production: A Platform Approach with Emerson T&M

The Session will cover the following topics:

• Overview of Emerson T&M( Formerly NI)
• Introduction to platform based approach
• Automated Device Validation(ADV) workflows for pre and post silicon validation
• Use cases and solutions for ADV for Power and Performance Measurements, PMICs, ADCs, DACs and RF ICs
• Automated Production Test (APT) with NI Platform
• Q&A

Online Interactive Webinar Series with Siemens EDA Tools by Siemens Team

The Session will cover the following topics:

• To build awareness around Electronic Design Automation (EDA) technologies and highlight how Siemens EDA's industry-leading products are shaping the future of semiconductor and electronic design

• A foundational element of design verification involves establishing correctness by construction, which will be explored through the Design Linting process. This will be succeeded by a discussion on the imperative for robust clock domain and reset domain crossings implementation and verification.
• The session will then transition to an exploration of Formal Verification technologies. These are emerging as a potent solution, facilitating early design analysis independent of testbench development. We will elucidate how formal verification contributes to mathematically proven design correctness, exhaustive verification coverage, and the early identification of corner-case scenarios.

Technical Online Session on IC Packaging: Trends & Challenges by Cadence Team

The Session will cover the following topics:

• Package Design Trends from Power modules to RF modules to Heterogeneous integration to Wafer level Chip Scale designs
• Need for EDA tools that can enable design capture and layout of different packages
• In-Design Analysis and Signoff

Technical (Online) Session on Regarding of PCB and IC Package Design in Modern Electronics by Siemens EDA

This Session provides a foundational understanding of IC Packaging and PCB Design.

• We will explore the electrical complexities of PCB & IC Package design in the context of high-performance systems and challenges involved around them. Participants will gain insights into leveraging PCB design and analysis tools, learning how to navigate manufacturability challenges and apply industry-leading best practices. The session will also showcase how sophisticated design platforms, such as Xpedition, can revolutionize design flow management.
• Furthermore, we'll explore the fundamental principles of Signal and Power Integrity in the context of both PCB and IC Packaging, demonstrating how simulation and analysis tools are indispensable for optimizing designs to achieve peak functional and performance efficiency.

• Cadence Genus Synthesis Overview
• Defining and Debugging failed SDC Constraints
• Multi-Mode Multi-Corner (MMMC) Synthesis Flow

• Integrating Floorplan Information
• Path Group and Cost Group Setup
• Physical-Aware Synthesis Execution

• Clock Gating Enablement
• Switching Activity Annotation (RTL/Gate)
• Power Optimization Attribute Configuration

• Scan Insertion and DFT Logic Integration
• Scan Chain Configuration and Connectivity
• Checking DFT Violation

Technical (Online) Session on Design. Verify. Innovate: Discover the Power of Analog Design

This Session covers a high-level understanding on Analog IP design flow right from designing transistor level schematics, enabling accurate circuit behaviour analysis, verification, and optimization before fabrication using industry standard EDA tools.

Online Session on Advanced IC Packaging Technologies and Facilities by Izmo Microsystems

The Session will cover the following topics:

• Introduction
• Overview of IC Packaging Evolution
• Advanced Packaging Technologies
• Izmo Packaging Facilities & Capabilities
• Case Studies

Technical (Online) Session on Integrated RTL to GDSII Design with Fusion Compiler by Synopsys Team

The Session will cover the following topics:

• Introduction to VLSI
• VLSI Design flow & Inputs used
• Fusion Compiler Synthesis Flow
• DFT - Design for Test
• Fusion Compiler P&R Flow
• Optimization technologies that deliver the best PPA / QoR
• Signoff checks and Tools (Formality, ICV, STARRC, PT)
• Demo

Technical (Online) Session on LNA Design using Keysight Advanced Design System

The Session will cover the following topics:

• DC Analysis
• Stability Network Design
• Bias Network Design
• Impedance Matching Network Design
• Layout & EM Simulation
• EM Circuit Cosimulation
• EM Simulation considerations for Non-Linear Simulations
• Non-Linear Simulations / Verification

Technical (Online) Session on Design-for-Test (DFT) by Siemens EDA

The Session will cover the following topics:

• Introduction to DFT: Basics of Design for Testability and its importance in testing of complex digital circuits.
• Understanding types of Manufacturing defects that can occur during the manufacturing process and their impact on chip functionality.
• Identify and analyse structural faults that can affect chip performance, including stuck-at faults, bridging faults, and delay faults etc.
• Develop an understanding of fault models, including their types, applications, and limitations, to facilitate effective testing and diagnosis.

Technical (Online) Session on Calibre EDA Tool - Day 1

The Session will cover the following topics:

Session 1: Introduction to Physical and Circuit Verification

• Importance of physical verification
• Intro to Calibre nmDRC, nmLVS, and PEX

Session 2: Using Calibre nmDRC/nmLVS

• Calibre basic concepts
• Running jobs using Calibre GUI
• Intro to Calibre RVE
• Calibre DRC process flow
• nmDRC HTML Reports
• Rule recipe customization
• Waiving and fixing results
• RVE features & LVL options

Technical (Online) Session on Calibre EDA Tool - Day 2

The Session details will cover the following topics:

Session 3: Calibre nmLVS Basics

• LVS process flow
• Job execution
• Texting & connectivity
• Troubleshooting shorts/opens
• Antenna & ERC checks

Session 4: Calibre Interactive - Advanced Features

• Interactive DRC/LVS
• Cell preservation
• Hierarchical cell analysis

Session 5: Calibre Parasitic Extraction (Calibre xRC)

• Parasitic network basics
• xRC netlist extraction & Calibre xRC flow
• Using RVE/DESIGNrev
• Reduction techniques

Technical (Online) Session: An Introduction to Physical Verification by Siemens EDA

The Session will cover the following topics:

• Master physical verification methodologies
• Implement efficient LVS comparison techniques
• Efficiently using Layout Viewing tool
• Using Calibre Interactive for Job Submission
• Improving Debug capabilities using Calibre RVE

Technical (Online) Session on Seamless RF Design using Cadence AWR

The Session will cover the following topics:

• RF Basics
• RF Applications
• RF designs using AWR

Technical (Online) Session on Hardware Emulation and Chip Validation by Siemens EDA

The Session will cover the following topics:

• Introduction to hardware emulation
• Importance of hardware emulation in modern chip design
• Exploration of use models and real-world applications on emulation platforms
• Discussion and Q & A session

Technical (Online) Session: An Introduction to Physical Design Implementation by Siemens EDA

The Session will cover the following topics:

• Describe end-to-end Physical Design flow
• Identify standard inputs and outputs for Physical Design
• Explain the processes of Placement, Clock Tree Synthesis (CTS), and Routing using Aprisa
• Understand PPA (Power, Performance, Area) constraints and Signoff procedures

Online Session on IC Packaging & Fab Capabilities by RRP Electronics Limited

The Session will cover the following topics:

• Introduction & Overview of RRP Electronics Ltd
• Pilot Production Facility and Design Capabilities
• Advanced Packaging Technologies (2.5D/3D integration), FOIP (Fan-Out Interposer Package), BGA packaging
• Prototype Fab Capabilities
• Discussion and Q & A session

Technical (Online) Session on Advanced DFT Features Using Cadence EDA Tools by Entuple Team - Day 1

The Session details will cover the following topics:

Session 1:

• Overview of DFT and advanced features in Cadence EDA tools
• Boundary Scan & Programmable Memory Built-In Self-Test (PMBIST)
• Demo: Setting up and running PMBIST

Session 2:

• Scan Compression techniques for reducing test data volume and test time
• Key configuration and flow setup
• Demo: Setting up and running Scan Compression

Technical (Online) Session on Advanced DFT Features Using Cadence EDA Tools by Entuple Team - Day 2

The Session details will cover the following topics:

Session 3:

• On-Product Clock Generation (OPCG) for at-speed test
• Defining and inserting the OPCG Macro
• Demo: Setting up and running OPCG

Session 4:

• Logic Built-In Self-Test (LBIST): Pattern generation for self-test
• Design considerations and flow
• Demo: Setting up and running LBIST

Online Technical Session on "2-Metal and 3-Metal Layer Process PDK" by SCL Team

The Session will cover the following topics:

• Introduction to SCL's 2-Metal/3-Metal SCL PDK in detail.
• Q & A Session

Four-Days Technical (Online) Session on Embedded Linux application development for MPSoC Device by CoreEL Team - Day 1

The Session will cover the following topics:

• Introduction to Zynq MPSoC Architecture
• Understanding with AXI Interconnect Standard
• Embedded System Design Flow using Xilinx Vitis IDE
• Extend the hardware system with Xilinx provided peripherals
• Creating a Simple Embedded Hardware Design
• Develop a basic embedded system for the target board on Vivado and write a basic C application using Vitis IDE to run on its exported hardware

Four-Days Technical (Online) Session on Embedded Linux application development for MPSoC Device by CoreEL Team - Day 2

The Session details will cover the following topics:

• Booting - How to implement the embedded system, including the boot process and boot image creation -First Stage Boot Loader - Demonstrates the process of developing, customizing, and debugging this mandatory piece of code
• Distinguish between asymmetric multiprocessing (AMP) and symmetric multiprocessing (SMP) environments
• Describe AMP and the OpenAMP framework and List the components of the OpenAMP framework
• Linux: A High-Level Introduction Linux Software Application Development Overview
• Building a Linux Application in the Vitis IDE

Four-Days Technical (Online) Session on Embedded Linux application development for MPSoC Device by CoreEL Team - Day 3

The Session details will cover the following topics:

• Introduction to Embedded Linux: Introduces Embedded Linux, including a brief architectural overview, as well as some of the reasons for its rising popularity as an embedded OS. Also introduces the concept of toolchains and cross-compilation.
• Embedded Linux Components: Describes the various components required for embedded Linux platforms (including the kernel image, root file system, and boot loaders) and how the components affect the booting of Linux on these platforms.
• Driving the PetaLinux Tool: Covers the functionality, inputs, and outputs of the PetaLinux tools as well as the project directory structure generated by the PetaLinux tools. Basic PetaLinux commands are also introduced.

Four-Days Technical (Online) Session on Embedded Linux application development for MPSoC Device by CoreEL Team - Day 4

The Session will cover the following topics:

• PetaLinux Tool Design Flow: Provides a brief description of the PetaLinux tool design flow and describes in detail various PetaLinux commands (including petalinux-create, petalinux-config, petalinux-build, petalinux-package, and petalinux-boot) and their example use cases.
• PetaLinux Application Development: Introduces core concepts for developing, customizing, and running software applications in an embedded Linux environment.
• Networking and TCP-IP:Explore the kernel configuration menu and identify configuration submenus that enable Linux TCP/IP networking,Experiment with the embedded web server on the Linux target,Build and experiment with web-based applications under Linux

An Introductory Online Session on Embedded Systems -From Product Design to PCB Layout by Renesas and Altium Team- Session 1

This session offers a hands-on introduction to our Embedded Systems program, designed to equip the next generation of engineers with real-world skills in embedded systems and PCB design-preparing them for high-impact roles in the electronics industry. Learn how to:

• Access and navigate Renesas QuickConnect Studio
• Use Renesas QuickConnect Kits to begin hands-on projects
• Activate and get started using your Altium Designer license
• Understand the structure of the new Embedded Systems curriculum
• Integrate the program into university courses or labs
• Follow a live demo of the tools and setup process

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

An Introductory Online Session on Embedded Systems -From Product Design to PCB Layout by Renesas and Altium Team- Session 2

This session offers a hands-on introduction to our Embedded Systems program, designed to equip the next generation of engineers with real-world skills in embedded systems and PCB design-preparing them for high-impact roles in the electronics industry. Learn how to:

• Access and navigate Renesas QuickConnect Studio
• Use Renesas QuickConnect Kits to begin hands-on projects
• Activate and get started using your Altium Designer license
• Understand the structure of the new Embedded Systems curriculum
• Integrate the program into university courses or labs
• Follow a live demo of the tools and setup process

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Technical (Online) Session on ATPG-based DFT flow using Cadence EDA Tool by Entuple Team - Day 1

The Session will cover the following topics:

Session-1:

• Overview of DFT and Cadence Modus DFT Solutions
• Design considerations and ATPG features in Modus
• Tool Demo: Setting up and run Modus ATPG Tool Flow

Session-2:

• Build and verify test structures
• Generating and writing test vectors
• Tool Demo: ATPG Vectors generation

Technical (Online) Session on ATPG-based DFT flow using Cadence EDA Tool by Entuple Team - Day 2

The Session will cover the following topics:

Session-3:

• Scan Chains Debugging
• Broken Scan Chains Analysis
• Tool Demo: Debugging with GUI/ TCL Interf

Session-4:

• Analyzing Sequence
• Debugging Test Pattern
• Tool Demo: Test vectors Simulation using Xcelium

Technical (Online) Session on Getting Started with Altium Designer by Renesas and Altium Team

This session walks you through accessing and activating Altium Designer licenses, with step-by-step instructions for both students and educators. Learn how to:

• Request and activate your Altium Designer license
• Navigate the registration and activation process
• Avoid common setup issues and delays

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Technical (Online) Session on Getting Started with QuickConnect Studio by Renesas and Altium Team

This session teaches students and educators how to set up QuickConnect Studio and educators to request for QuickConnect Kits for hands-on, project-based learning in embedded systems. Learn how to:

• Create a QuickConnect account and access the platform
• Guide educators to request for QuickConnect kits using form
• Navigate the QuickConnect Studio's interface and workflows

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Two Days Technical (Online) session on Questa Static Formal verification solutions by CoreEL Team - Day 1

The Session will cover the following topics:

• Introduction to FPGA tool flow
• Need for Early Verification
• Formal Adaptation & Overview of Questa Formal tools
• Intro to Questa Lint, Lint Workflow, Checks Methodology and Goals, Questa Result Analysis and Hands on Tool Demonstration
• Intro to Questa Inspect, Workflow, Predefined Checks for Common Problems, Inspect Benefits and Hands on Tool Demonstration

Two Days Technical (Online) session on Questa Static Formal verification solutions by CoreEL Team - Day 2

The Session will cover the following topics:

• Intro to Questa Increase coverage, workflow, increase coverage benefits etc.
• Checks for coverage exclusions.
• Questa increase coverage with Questa Sim and Hands on Tool Demonstration
• Intro to Questa CDC, CDC Workflow, Need for CDC Verification, Common CDC Issues Analysis and Debugging and Hands on Tool Demonstration

Technical (Online) Session on Introduction to Analog Design Concepts by ChipIN Team

The Session will cover the following topics:

• Fundamental concepts related to analog circuit design.
• Short channel effects and impacts over circuit design.
• Demo: Drawing a schematic in schematic XL editor.

Technical Online Session on Parametric Extraction with SCL 180nm Technology and Introduction to High-Gain Telescopic OpAmp Circuit Design by ChipIN Team

The Session will cover the following topics:

• High-Gain Telescopic OpAmp Circuit Design (Theory Session)
• Hands on Lab Session on High-Gain Telescopic OpAmp Circuit Design
• Lab Session on SCL 180nm (Bi-metal Process) - Parametric Extraction Using Cadence Virtuoso.

Technical Online Session on High-Gain Telescopic OpAmp Circuit Design Pre-Layout Simulations and Introduction to Analog Custom Layout Design Concepts by ChipIN Team

The Session will cover the following topics:

• Pre layout simulations of High-Gain Telescopic OpAmp Circuit Design.
• Custom Layout of High-Gain Telescopic OpAmp Circuit Design in Layout suite XL.
• LVS, DRC and layout validation techniques etc.

An Introductory Online Session on Embedded Systems -From Product Design to PCB Layout by Renesas and Altium

This session offers a hands-on introduction to Embedded Systems program, designed to equip the next generation of engineers with real-world skills in embedded systems and PCB design. Learn how to:

• Access and navigate QuickConnect Studio
• Use QuickConnect Kits to begin hands-on projects
• Activate and get started using your Altium Designer license
• Understand the structure of the new Embedded Systems curriculum
• Integrate the program into university courses or labs
• Follow a live demo of the tools and setup process

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Technical (Online) Session on Altium Designer- Key Concepts and Practices

This session introduces students to the fundamentals of PCB design and the Altium ecosystem, helping them understand the complete design process from schematic creation to PCB layout and collaboration through Altium 365.

• Discover the PCB design workflow, including schematics, footprints, layers, and stack-up.
• Get hands-on insights into Altium Designer and Altium 365 and learn how these tools enable collaboration and cloud-based design.
• Understand Altium 365 licensing and workspace activation.

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Technical (Online) Session on Virtual Labs, Real Learning: Exploring Simulation and Debug by Cadence Team

The Session will cover the following topics:

• VLSI flow
• DV role, Types of Design Verification Methodologies
• Introduction to the Cadence tool for Simulation and Debug
• Examples to run RTL simulation and debug
• Q&A

Technical (Online) Session on Getting Started with Renesas QuickConnect Studio

This session teaches students and educators how to set up QuickConnect Studio and educators to request for QuickConnect Kits for hands-on, project-based learning in embedded systems. Learn how to:

• Create a QuickConnect account and access the platform
• Guide educators to request for QuickConnect kits using form
• Navigate the QuickConnect Studio's interface and workflows

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Technical (Online) Session on "VEGA Processors: India's Indigenous RISC-V Based Computing Revolution"

This session will introduce the core principles of the RISC-V Instruction Set Architecture (ISA) and explore the different processor variants within the RISC-V ecosystem. It will also discuss the range of peripheral IPs commonly integrated into SoC designs. Participants will gain an understanding of the architecture and integration approach of VEGA-based SoCs, as well as the design and verification processes adopted for these systems. The session will further highlight the validation strategies and methodologies employed to ensure dependable and high-quality SoC development.

Two-Days Technical (Online) Session on TCL Script: Automation for Cadence's Xcelium Tool by Entuple Team - Day 1

Session-1: Introduction & Overview

• Introduction to the Xcelium Tcl console and interactive modes
• Tcl syntax essentials for simulation control
• Navigating design hierarchy and querying objects
• Tool demo: Use Tcl commands to explore design data

Session-2: Automation Simulation setup and Demo

• Environment and path configuration
• Automating simulation run, compile, and elaboration steps
• Handling files and variables for testbench setup

Two-Days Technical (Online) Session on TCL Script: Automation for Cadence's Xcelium Tool by Entuple Team - Day 2

Session-3: Debugging and Analysis

• Driver tracing and breakpoint control via Tcl
• Glitch debug and waveform inspection commands
• Handling simulation hangs or infinite loops
• Tool Demo: Use Tcl to trace signal drivers and debug a simulation

Session-4: Scripting and Tool Demo

• Save and restart simulation sessions using Tcl procedures
• Deposit and force command applications
• Scripting repetitive debug tasks and report generation
• Tool demo: Create a Tcl macro to capture checkpoints, and auto-generate debug reports

Technical (Online) Workshop on Altium- Mastering the Fundamentals

This hands-on workshop covers the complete PCB design process using Altium Designer and Altium 365, from schematic creation to manufacturing files and cloud collaboration.

• Quick revision of PCB fundamentals and Altium overview
• Creating a schematic, placing components, and running ERC
• Translating schematic to PCB and understanding layer stack-up
• Component placement, routing, and performing DRC
• Generating and verifying Gerber files
• Exploring Altium 365 for project sharing and collaboration

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Online Session on Renesas QuickConnect Studio Kick-off: Building and Customising Your First Blinky LED App

This session will teach students and educators how to use Renesas QuickConnect Studio, a cloud-based development environment and guide them through creating the first embedded application - a simple "Blinky LED" program using the QuickConnect Beginners Kit 2.0. Participants will learn how to set up their workspace, develop and upload code to the QuickConnect board, and explore ways to customize and troubleshoot their project for deeper understanding.

• Workspace Setup and First Project: Learn about the QuickConnect Studio and Beginners Kit 2.0, set up your cloud-based workspace, and create your first project directly in the browser.
• Code Development & Upload: Develop, compile and upload your LED blink program using the QuickConnect Studio and install the Segger tool required for uploading the program to the microcontroller board.
• Verification and Customization: Verify LED behaviour, experiment with customizing blink patterns and timing, and explore common troubleshooting techniques to ensure your project runs smoothly.

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Technical (Online) Session on Altium Workshop - Key Concepts and Practices by Renesas-Altium.

Fundamentals of PCB design and the Altium ecosystem, helping them understand the complete design process from schematic creation to PCB layout and collaboration through Altium 365.

• Discover the PCB design workflow, including schematics, footprints, layers, and stack-up.
• Get hands-on insights into Altium Designer and Altium 365 and learn how these tools enable collaboration and cloud-based design.
• Understand Altium 365 licensing and workspace activation.

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Technical Online session on Component Library Creation and Management - Mastering Custom Parts in Altium Designer

This workshop teaches how to build, organize, and use custom components in Altium Designer for consistent, error-free PCB design.

• Understanding libraries, symbols, footprints, and why they matter
• Creating schematic symbols and IPC-compliant footprints from scratch
• Linking symbols and footprints to build integrated libraries
• Using custom libraries in schematic projects for smoother design flow

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Technical Online session on High-Speed PCB Design Fundamentals by Renesas-Altium

This session introduces the essential concepts of high-speed PCB design and teaches how to handle impedance, routing, and signal integrity inside Altium Designer.

• Understanding when a PCB becomes "high-speed" and key challenges
• Setting stack-up and controlled impedance for single-ended and differential lines
• Creating and routing differential pairs with proper length matching
• Ensuring good return paths and avoiding SI issues like EMI, reflections, and crosstalk
• Setting high-speed rules, running DRC, and validating tuned traces

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Technical Online Session on Post-Layout Simulations with Core Using Cadence Virtuoso EDA Tool, IO Pad-Ring & Seal-Ring Integration with Core using Cadence Virtuoso EDA Tool.

The Session will cover the following topics:

• Hands-on Lab session on post-layout simulations to validate performance
• The Session Covers Designing pad-ring, seal-ring, dummy fill and related blocks

Technical Online Session on Full-Chip Simulation and Physical Verification Using Cadence Virtuoso and Siemens Calibre Tools

The Session will cover the following topics:

• The session will cover core +IO simulations of High-Gain Telescopic OpAmp Circuit Design.
• The Session will cover Final full-chip verification.

Technical (Online) Session on "Testing of Chip on Board (CoB) Packaged Devices" by SCL Team

This Session would cover Testing of Chip on Board (CoB) Packaged Devices in detail.

Technical (Online) Session on Board and Remote Farm Debugging: Troubleshoot Like a Pro

This session focuses on mastering both local and remote debugging techniques for embedded boards and remote farm environments. Participants will learn how to capture and analyse print logs locally, and how to efficiently debug remotely using breakpoints, variable watch, and call stacks. This session will also cover practical debugging workflows to identify, isolate, and fix issues effectively.

• Local System Debugging: Learn how to display and manage print data for efficient system logging and real-time tracking.
• Remote Farm Debugging: Understand debugging fundamentals - breakpoints, variable watch, call stack analysis, and key control options (steps-in, step-out, continue, stop).
• Efficient Troubleshooting: Apply structured debugging strategies to streamline issue identification and resolution in both local and remote setup.

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Technical (Online) Session on "Practical TCL Scripting: Frequently Used Commands in Cadence Xcelium Simulation Tool" by Entuple Team

The Session will cover the follwoing topic's:

• Essential Tcl Commands in Xcelium Simulation (Basics & Control)
• Waveform, Signal, and Database Control Commands
• Tcl Automation for Debugging, Reports, and Reusable Simulation Scripts
• Tool Demo: Automate Xcelium Debug & Simulation Using Tcl Commands

Technical (Online) Workshop on "Altium - Mastering the Fundamentals" by Renesas-Altium

This workshop covers the complete PCB design process using Altium Designer and Altium 365, from schematic creation to manufacturing files and cloud collaboration.

• This session is suitable for both students and faculty members who are new to PCB design or Altium Designer.
• It is also useful for educators looking to understand the complete PCB design workflow for academic and training purposes.
• Quick revision of PCB fundamentals and Altium overview
• Creating a schematic, placing components, and running ERC
• Translating schematic to PCB and understanding layer stack-up
• Component placement, routing, and performing DRC
• Generating and verifying Gerber files
• Exploring Altium 365 for project sharing and collaboration

Technical (Online) Session on "Renesas QuickConnect Studio: Building and Customising Your First Blinky LED App" by Renesas-Altium.

This session will teach students and educators how to use Renesas QuickConnect Studio, a cloud-based development environment.

• Workspace Setup and First Project: Learn about the QuickConnect Studio and Beginners Kit 2.0, set up your cloud-based workspace, and create your first project directly in the browser.
• Code Development & Upload: Develop, compile and upload your LED blink program using the QuickConnect Studio and install the Segger tool required for uploading the program to the microcontroller board.
• Verification and Customization: Verify LED behaviour, experiment with customizing blink patterns and timing, and explore common troubleshooting techniques to ensure your project runs smoothly.

Technical Online Session on Formal Verification-Basics by Cadence Team

The session will covers the following topics :

• What is Formal verification?
• Formal Property Checking
• Formal Activity Goals
• SVA Verification directives
• What are assertions, assumptions and covers?
• Formal vs simulation
• Formal proof results
• What is COI?
• Complexity and size problem
• Focus area for formal
• Demo
• Summary
• Q&A

Two-Days Technical (Online) Session on "Pads professional and Analysis" by CoreEL Team - Day 1

The session will covers the following topics :

• Library Management & Schematic Design Training
  • Creating and accessing a new library
  • Understanding library flow
  • Navigating the GUI
  • Creating schematic symbols, padstacks, and footprints
  • Building parts
  • Library services
  • Part Quest
  • Group discussion / Q&A
• Designer -Schematic Creation
  • Project creation, Library mapping, Display and backup settings
  • Component placement strategies, Net connections, Creating groups or clusters
  • Forward annotation to PCB layout
  • Constraint management, BOM (Bill of Materials) creation
  • Q&A

Two-Days Technical (Online) Session on "Pads professional and Analysis" by CoreEL Team - Day 2

The Session will covers the following topics :

• PADS Professional PCB Layout Training
  • Defining board outlines, Component placement strategies
  • Display control settings, Manual routing and semi-auto routing
  • Constraint Manager & Editor, Editor controls
  • Design rule checks (DRC) and verification
  • Manufacturing output generation (Gerber, ODB++ etc.)
  • Group discussion / Q&A
• Analysis Training
  • Power Integrity analysis: DC drop Analysis, Thermal Analysis, AC analysis (PDN)
  • Signal integrity analysis : Interactive simulation, General batch wizard, Termination optimization, DDRx analysis, SerDes batch analysis, S-parameter extraction etc.

Technical (Online) Session on "From Transistors to VIP: The Verification Journey in Chip Design" by Cadence Team

The session covers the following topics :

• From Transistors to Chips
• Breaking down a Mobile
• Protocols in Chip Design
• Chips Design Flow and Why Verification is needed?
• Introduction to VIP
• How VIP works in a Testbench
• Q&A

Technical Online session on Component Library Creation and Management - Mastering Custom Parts in Altium Designer

The session covers the following topics :

• This session is intended for advanced learners who already understand basic schematics and PCB design.
• Understanding libraries, symbols, footprints, and why they matter
• Creating schematic symbols and IPC-compliant footprints from scratch
• Linking symbols and footprints to build integrated libraries
• Using custom libraries in schematic projects for smoother design flow

Technical Online Session on "Renesas QuickConnect Studio Foundations: Create and Troubleshoot" by Renesas-Altium Team

The session covers the following topics :

• Code Development & Upload: Develop, compile and upload your LED blink program using the QuickConnect Studio and install the Segger tool required for uploading the program to the microcontroller board.
• Verification and Customization: Verify LED behaviour, experiment with customizing blink patterns and timing, and explore common troubleshooting techniques to ensure your project runs smoothly.
• Local System Debugging: Learn how to display and manage print data for efficient system logging and real-time tracking.

Technical (Online) Session on Low Power Verification with CPF Using Cadence Conformal by Entuple Team

The session covers the following topics :

• Introduction to Low Power Verification
• CPF Concepts & Power Intent Modeling
• Conformal Low Power Verification Flow
• Tool Demo: Conformal Low Power - CPF-Based Verification Demo
• Q and A

Techincal (Online) Workshop on "Altium - Key Concepts and Practices" by Renesas-Altium

This workshop introduces students to the fundamentals of PCB design and the Altium ecosystem, helping them understand the complete design process from schematic creation to PCB layout and collaboration through Altium 365.

• This is a beginner level session and does not require any prior knowledge of PCB design or Altium.
• Altium Designer License is required and the latest version tool should be installed and activated before the workshop.
• Students/Faculties who are completely new to PCBs and design tools should attend this session.
• Discover the PCB design workflow, including schematics, footprints, layers, and stack-up.
• Get hands-on insights into Altium Designer and Altium 365 and learn how these tools enable collaboration and cloud-based design.
• Understand Altium 365 licensing and workspace activation.
• Q & A Session

Technical (Online) Session on "Renesas QuickConnect Studio: Code Customization for Switch and LED Control" by Renesas-Altium

This session covers understanding push button behavior and switch bouncing, implementing software debouncing techniques in QuickConnect Studio, and developing, compiling, and uploading a button-controlled LED ON/OFF program, followed by verifying stable LED operation through button press testing and debounce timing adjustments while exploring common troubleshooting techniques to ensure reliable performance.

• Button Interface & Debouncing: Understand push button operation, identify switch bouncing issues, and implement software debouncing techniques using QuickConnect Studio.
• Code Development & Upload: Develop, compile, and upload a button-controlled LED ON/OFF (toggle) program using QuickConnect Studio and the required programming tools for the microcontroller board.
• Verification & Troubleshooting: Verify LED behavior using debounced button presses, adjust debounce timing, and explore common issues and fixes to ensure stable and reliable operation.

Technical (Online) Session on "High-Speed PCB Design Fundamentals" (Advanced Level) by Renesas-Altium

This session introduces the essential concepts of high-speed PCB design and teaches how to handle impedance, routing, and signal integrity inside Altium Designer.

• This session is intended for advanced learners who already understand PCB layout fundamentals.
• Altium Designer License is required and the latest version tool should be installed and activated before the workshop.
• It is especially useful for those looking to strengthen their knowledge of signal integrity and high-speed routing practices in Altium Designer.
• Understanding when a PCB becomes "high-speed" and key challenges
• Setting stack-up and controlled impedance for single-ended and differential lines
• Creating and routing differential pairs with proper length matching
• Ensuring good return paths and avoiding SI issues like EMI, reflections, and crosstalk
• Setting high-speed rules, running DRC, and validating tuned traces

A Preliminary Getting Started Online Session by Keysight on 12-Feb-2026 (Thursday) at 02:30 PM

This session focuses on Installing the Keysight EDA tools, accessing centrally hosted EDA licenses, setting up environment variables, support related, etc.

Online Interactive Session on SolvNet Helpdesk by Synopsys Team on 17-Feb-2026 (Tuesday) at 02:30 PM

The Session will cover the following topics:

• How to register on SolvNet. 
• How to raise a support ticket on SolvNet for various issues (e.g., tool download, tool features related, design support related, etc.)
• Accessing documentation for any Synopsys product on SolvNet.
• Locating tool binaries, SCL, and other related resources.
• How to install Synopsys tools.
• Finding training content (including self-paced and university curriculum modules)

Technical (Online) Session on "Renesas QuickConnect Studio Foundations: Create and Troubleshoot" by Renesas-Altium

This session covers developing, compiling, and uploading an LED blink program using QuickConnect Studio, including installing and using the Segger tool to program the microcontroller board, followed by verifying correct LED behavior through customization of blink patterns and timing while exploring common troubleshooting techniques to ensure smooth operation, and concluding with local system debugging practices that focus on displaying and managing print data for effective system logging and real-time monitoring.

• Code Development & Upload: Develop, compile and upload your LED blink program using the QuickConnect Studio and install the Segger tool required for uploading the program to the microcontroller board.
• Verification and Customization: Verify LED behaviour, experiment with customizing blink patterns and timing, and explore common troubleshooting techniques to ensure your project runs smoothly.
• Local System Debugging: Learn how to display and manage print data for efficient system logging and real-time tracking.

A Preliminary Getting Started Online Session by Ansys on 19-Feb-2026 (Thursday) at 11 AM

This session covers the following topics:

• Introduction of Ansys (Part of Synopsys)
• Semiconductor Software PORTFOLIO
• Products Part of C2S Program
• Technical overview of each products, download and installation.
• Demo - Installation and Download
• OS and System Requirements
• Queries and Support Contact

Two-Days Technical (Online) Session on SoC-Level Low-Power Verification Using Cadence Conformal Tool by Entuple Team - Day 1

Session 1: SoC-Level Low-Power Verification at Synthesis Stage Using Cadence Conformal Low Power (CLP) tool (Date: 25th Feb 2026, Time: 3:30pm to 5pm)

Agenda:

• Low-Power Verification Fundamentals & CPF Modeling at RTL
• Power Domains, Isolation, Retention & Power Switch Concepts
• Conformal Low Power (CLP) Synthesis-Stage Verification Flow & Structural Checks
• Tool Demo, Key Takeaways & Q&A

Two-Days Technical (Online) Session on SoC-Level Low-Power Verification Using Cadence Conformal Tool by Entuple Team - Day 2

Session 2: Low-Power Verification at PNR Stage Using Cadence Conformal Low Power (CLP) tool (Date: 26th Feb 2026, Time: 3:30pm to 5pm)

Agenda:

• Power Intent Preservation from RTL to Physical Design
• Post-P&R Isolation, Retention & Always-On Connectivity Verification
• Conformal Low Power (CLP) P&R-Stage Verification Flow & Physical Integrity Checks
• Tool Demo, Sign-Off Considerations & Q&A