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IIT Indore Instruction Enhancement Programme (IEPs) Resources - Session 3

# MATERIALS
1 Case Study_ Architectural Level Integration of SRAM Memory IP-002

2 Industry Expert Talk on Memory Design, It's Role & Design Challenges for AI Applications by Dr. Vishal Sharma

3 LS-5 (part-1) I_O Padding & GDS-II File Generation on Cadence Virtuoso Layout XL

4 LS-5 (part-2) I_O Padding & GDS-II File Generation on Cadence Virtuoso Layout XL

5 LS-6 (Part-1)_ 6T-SRAM Bitcell Design on Cadence Virtuoso

6 LS-6 (Part-2)_ 6T-SRAM Bitcell Design on Cadence Virtuoso-005

7 LS-6 (Part-3)_ 6T-SRAM Bitcell Design on Cadence Virtuoso

8 LS-7_ SRAM Peripheral Circuitry_ Precharge Circuit, Decoder, Multiplexer, Sense Amplifier, Controller

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