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IIT Indore Instruction Enhancement Programme (IEPs) Resources - Session 5

# MATERIALS
1 Demo Lab Session on Fully Automated SRAM Bitcell Analysis & Graphical Floorplan Development of Memory Subsystem by Spectral Design and Test Inc

2 Industry Expert Talk on Conflux of Embedded Memory & Logic Architectures by Jayachandar Polisetty

3 Industry Expert Talk on Designing Radiation Hardened SRAM Bit Cells by Dr. Pramod Kumar Bharti,

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