C2S

14 Design submitted for Fabrication in MPW Manner at 180nm, SCL Mohali in April’2025 by ChipIN Centre

MPW SHUTTLE - II TO SCL THROUGH CHIPIN CENTRE

Sl.No	Silicon Number	Institution Name	Description of IC
FOUR-METAL PROCESS DESIGN SUBMISSIONS
1	C2S0031	SVNIT Surat	ECG Artifact Reduction and Arrhythmia Detection
2	C2S0047	NIT Calicut	Programmable Gain Amplifier (PGA)
3	C2S0048	University of Calcutta	Low Power Analog Front End for Air Flow Detection added with additional sub circuits
4	C2S0050	IIT Ropar	Digital PLL and Pseudo Random Binary Sequence Generators
5	C2S0054	IIT (ISM) Dhanbad	Low/ultra-low power analog VLSI memristor emulator
6	C2S0056	NIT Puducherry	ASIC Implementation of 16 bit approximate multiplier with improved accuracy
7	C2S0057	NIT Puducherry	ASIC Implementation of 12 bit Fixed point division
8	C2S0061	Parala Maharaja Engineering College	High-Performance Approximate Multiplier IC for Energy-Efficient CNN Execution in ASICs
SIX-METAL PROCESS DESIGN SUBMISSIONS
9	C2S0025	IIT Roorkee	RF Receiver: Low Noise Amplifier, 4 Path Mixer, and 4 phase clock generation from reference LO, RF Receiver operating from 1.5 to 2.6 GHz for Qubit Readout, Ring Oscillator
10	C2S0037	NIT Warangal	CMOS temperature sensor and LDO
11	C2S0049	IIT Ropar	Voltage Controlled Ring Oscillator, Phase Locked Loop, Fire neuron and on chip inductors
12	C2S0053	IET DAVV	Operational Amplifier Design for a Filter
13	C2S0059	Dr.Mahalingam College of Engineering and Technology	High gain, Low power, Low Noise Operational Transconductance Amplifier for Neural Signal Processing
14	C2S0060	Dr.Mahalingam College of Engineering and Technology	Single channel High-gain, Low-power, Low- Noise Neural Signal Amplifier

Announcement for Tape-out submissions for MPW Shuttle-II at 180nm, SCL Mohali through ChipIN Centre for Participating Institutions under C2S Programme for fabricating them in April 2025

ChipIN Centre (C-DAC Bangalore) is now accepting design tape-outs for MPW Shuttle-II at 180nm, SCL Mohali, from Participating Institutions (PIs) under the C2S (Chips to Start-up) Programme for fabricating them in April 2025 as per following timelines.

#	MPW Shuttle - II	Timelines
1	MPW Shuttle – II Announcement by ChipIN Centre for fabrication of designs at 180nm, SCL Mohali by Participating Institutions (PI)	03rd January 2025
2	PIs to submit request to ChipIN Centre for obtaining the Silicon number from SCL.	08th January 2025
3	ChipIN Centre to provide Silicon number to the PI	13th January 2025
4	Submission of the initial version of design by PIs to ChipIN Centre as per guidelines of Design Tapeout Submission Form (i.e. Si Number, report on DRC clean, antenna check etc.)	27th January 2025
5	ChipIN Centre to provide a Verification Report to PIs for initial version of designs submitted by PIs.	31st January 2025
6	PIs to submit the final version of fab-ready design/ GDS to ChipIN Centre addressing the issues, if any, highlighted in the Verification Report.	21st February 2025
7	Submission of designs of PIs by ChipIN Centre to SCL for fabrication.	28th February 2025
8	The designs to go in the fabrication lot at SCL Mohali	April 2025
9	Receiving of fabricated designs in packaged form by the PIs	31st December 2025

Design Tapeout Submission Process by Participating Institutions (PIs)

Step 1: Obtaining Silicon Number by PIs

The PIs to send an e-mail to ChipIN Centre to get the Silicon Number with duly filled Silicon_Number_Generation_Form (see attachment) by 08th January 2025. Please go through the Silicon_Numbering_Table (see attachment) for various code details to be used for filling it.
ChipIN Centre to provide Silicon number to the PI.

Step 2: Submission of Design

Participating Institutions (PIs) to provide their design details in the Design Tapeout Submission Form (DTSF) and Process Information Sheet (PIS sheet) for projects intended for tapeout at 180nm, SCL Mohali.
The DTSF provides information on various items, which must be considered when a design is submitted by PI to ChipIN Centre.
All the columns in the PIS sheet must be filled with the drop-in information, wherever provided. At places, where drop-in is not given, designer must write as per the column description only.

Design Tapeout Submission Form (DTSF)

(see attachment)

Process Information Sheet (PIS sheet)

(see attachment)

General Guidelines

1.0 Data Format and Communication:

Acceptable database format is GDSII only.
Complete database must be sent through e-mail to chipin@cdac.in. Do not provide any Google Drive link.
The communication has to be addressed through e-mail at:
- To: chipin@cdac.in
- CC: venkatark@cdac.in, viviand@cdac.in, support.c2s@meiy.gov.in
ChipIN Centre,
C2S Programme,
C-DAC Bangalore, Opp. HAL Aeroengine Division,
Old Madras Road, Byappanahalli,
Bengaluru - 560 038.

2.0 Layout Grid

Minimum grid size used in the GDSII must be integer multiple of 0.005 µm.
Final GDSII window (including seal ring) must have Bottom left corner at (0,0) coordinate and the Top-Right corner coordinate must be rounded off to closest even number and it should be without any decimal places i.e., 10102 µm or 10100 µm for the case if coordinate comes at 10101.395 µm.

3.0 Design Kit

Do not rename cell names used in cell library.
Do not use library cell name for custom designed cells.
Do not edit standard cell library and I/O library.

4.0 Design Verification

The PIs to provide a clean GDSII database w.r.t. DRC, Density and Antenna rules.
Before taping out the data, please provide checksum for GDSII file. Save the checksum value and byte count in a file, so that the same can be crosschecked at our end. e.g. cksum EDU0001_01012016_v1.gds 12345678 204 EDU0001_01012016_v1.gds
For GDSII integrity check while data transfer MD5 checksum is must and need to be provided in addition to checksum so that the same can be crosschecked at our end. For calculating MD5, just open Linux terminal and type: md5sum ‘filename’ e.g. md5sum SC0001-0E_25012023_v1.gds
GDSII name and Top cell name format: silicon_no_date_version.gds (date format should be ddmmyyyy) and top cell name should be "silicon number" only.
All the reports should be named as GDSII name. For instance, siliconnum_date_version_drc.rpt, siliconnum_date_version_drc.summary, siliconnum_date_version_ant.rpt etc.
All the columns in the Process Information Sheet (PIS sheet) must be filled with the drop-in information wherever provided. At places where drop-in is not given, designer must write as per the column description only.

5.0 Tapeout Checklist

#	Device Related Information	Yes/No
1	GDSII database provided
2	Silicon Number with PCI is mandatory. GDSII for this is included in the PDK. (Layer revision block may be placed if space permit)
3	Seal Ring with GND connection inserted?
4	Is DRC along with dummy fill Report clean?
5	Is Antenna along with dummy fill Report clean?
6	Dummy Fill done
7	Grid size 0.005µm used for layout
8	Whether Pads connected till top metal (TOP_M)?
9	Final Chip Origin should be at (0,0) after seal ring insertion.
10	Process Information Sheet duly filled?

6.0 Reports to be Included

1	Final DRC run Reports (Result database including density logs, summary, transcript, runset version)
2	Final Antenna Report (Result database, summary, transcript, runset version)
3	Devices type (or legal devices) used in layout report
4	Stream out log files
5	List of 3rd party IP used (If any with prior approval from SCL)
6	List of SCL IP used (If any with prior approval from SCL)
7	List of all legal layers used before silicon number insertion in Excel Format (Layer Name + layer number + datatype)
8	Coordinate of Silicon number
9	Process Information Sheet (Attached PIS Excel)

7.0 Tape-out and Packaging Related Checklist

#	Tape-out and Packaging Related Checklist	Please Tick / Specify
1	Mention the Die size including seal ring. Options supported: 2 x 2 mm², 3 x 3 mm², 4 x 4 mm², or 5 x 5 mm² (No other size is supported in the current tapeout under this program) For sizes greater than 5 x 5 mm² ChipIN will contact SCL’s PPG.	Specify 2 x 2 mm² or 3 x 3 mm² or 4 x 4 mm² or 5 x 5 mm²
2	The design should have a seal ring around it. The distance between chip boundary to seal ring should be a minimum of 10µm with DRC Clean.
3	The seal ring is connected to VSS (Ground).
4	No. of pins for Packaging the IC (Currently no. of pins should not be more than 100 for packaging).	Specify the No. of Pins
5	Package selected for packaging (Refer Serial No. 8) - Specify the Package Serial Number
6	The minimum pitch between two adjacent bond pads is 90µm for all bond pads.

8.0 Preferred Die Size and plastic packages (Chip-on-Board<CoB> Packaging Options)

Serial No.	Die Size (mm)	Package Size (mm)	Pin Count	Package Lead Pitch (mm)	CoB Package Type
1	2.0 x 2.0	4.0 x 4.0	16	0.65	QFN/DIP
2	3.0 x 3.0	5.0 x 5.0	16	0.8	QFN/DIP
3	2.0 x 2.0	4.0 x 4.0	24	0.65	QFN/DIP
4	3.0 x 3.0	5.0 x 5.0	24	0.65	QFN/DIP
5	3.0 x 3.0	5.0 x 5.0	28	0.5	QFN/DIP
6	2.0 x 2.0	5.0 x 5.0	32	0.5	QFN/DIP
7	3.0 x 3.0	5.0 x 5.0	32	0.5	QFN/DIP
8	2.0 x 2.0	7.0 x 7.0	48	0.5	QFN/DIP
9	3.0 x 3.0	7.0 x 7.0	48	0.5	QFN/DIP
10	2.0 x 2.0	9.0 x 9.0	64	0.5	QFN/DIP
11	3.0 x 3.0	9.0 x 9.0	64	0.5	QFN/DIP
12	4.0 x 4.0	7.0 x 7.0	48	0.5	QFN/DIP
13	5.0 x 5.0	7.0 x 7.0	48	0.5	QFN/DIP
14	4.0 x 4.0	9.0 x 9.0	64	0.5	QFN/DIP
15	5.0 x 5.0	9.0 x 9.0	64	0.5	QFN/DIP
16	4.0 x 4.0	10.0 x 10.0	72	0.5	QFN/PGA
17	5.0 x 5.0	10.0 x 10.0	72	0.5	QFN/PGA
18	4.0 x 4.0	12.0 x 12.0	80	0.5	QFN/PGA
19	5.0 x 5.0	12.0 x 12.0	80	0.5	QFN/PGA
20	4.0 x 4.0	12.0 x 12.0	88	0.5	QFN/PGA
21	5.0 x 5.0	12.0 x 12.0	88	0.5	QFN/PGA
22	4.0 x 4.0	14.0 x 14.0	100	0.5	QFN/PGA
23	5.0 x 5.0	14.0 x 14.0	100	0.5	QFN/PGA