22 Designs submitted for Fabrication in MPW Manner at 180nm, SCL Mohali in July'2025 MPW Shuttle by ChipIN Centre

MPW SHUTTLE - III TO SCL THROUGH CHIPIN CENTRE

Sl.No	Silicon Number	Institution Name	Description of IC
FOUR-METAL PROCESS DESIGN SUBMISSIONS
1	C2S0006	SVNIT Surat	An accelerator employing a Multiplier-Adder-Tree-Accumulator based architecture
2	C2S0058	NIT Puducherry	Convolutional Neural Network for Keyword Spotting Chip
3	C2S0068	University of Calcutta	Air flow detector module in HVAC system (FLOWDECH)
4	C2S0079	IIT Jammu	Low power, high gain amplifier design for Sensing Block of iPACE (pacemaker) Chip
5	C2S0080	IIT Jammu	Leakage Power Attack Resilient 8T SRAM
6	C2S0081	IIT Ropar	The circuit integrates two primary components: 1. 10 Programmable PRBS (Pseudorandom Binary Sequence) Generators 2. High-Speed Dynamic Comparators
7	C2S0083	IIT (ISM) Dhanbad	VLSI memristor emulator based Multilayer Neural Networks (MNN)
8	C2S0084	IIT (ISM) Dhanbad	Biological synapse designed as a low/ultra-low power analog VLSI memristor emulator
9	C2S0087	Model Engineering College, Thrikkakara	Convolutional neural network based object detection
10	C2S0088	Model Engineering College, Thrikkakara	Kalman Filter
11	C2S0095	NIT Calicut	Real-time traction control system
12	C2S0097	NIT Meghalaya	FSM Block (Finite State Machine), at a clock frequency of 100 kHz. DAC Block (8-bit R-2R DAC)
13	C2S0098	NIT Puducherry	Real-time audio processing
14	C2S0099	PES University	Expiry Identifier
15	C2S0100	PES University	A Phase-Locked Loop (PLL)
16	C2S0101	SVNIT Surat	ReMAC architecture
SIX-METAL PROCESS DESIGN SUBMISSIONS
17	C2S0033	IIT Gandhinagar	Chip contains in total 10 macros with Ring oscillator, Muxs and Demuxs.
18	C2S0034	IIT Gandhinagar	Dual Interlocked (DICE) and Double Port-Dual Interlocked (DPDICE) storage cells
19	C2S0082	IIT Ropar	Neuron circuit
20	C2S0089	North Eastern Hill university	Early-stage Identification of Red Spider Mite
21	C2S0093	NIT Arunachal Pradesh	Digital Control System
22	C2S0094	NIT Arunachal Pradesh	Digital circuits-based clock generator

Announcement for Tape-out submissions for MPW Shuttle-III at 180nm, SCL Mohali through ChipIN Centre for Participating Institutions under C2S Programme for fabricating them in July’ 2025

ChipIN Centre (C-DAC Bangalore) is now accepting design tape-outs for MPW Shuttle-III at 180nm, SCL Mohali, from Participating Institutions (PIs) under the C2S (Chips to Start-up) Programme for fabricating them in July 2025 as per following timelines.

#	MPW Shuttle - III	Timelines
1	MPW Shuttle – III Announcement by ChipIN Centre for fabrication of designs at 180nm, SCL Mohali by Participating Institutions (PI)	27th March 2025
2	PIs to submit request to ChipIN Centre for obtaining the Silicon number from SCL.	04th April 2025
3	ChipIN Centre to provide Silicon number to the PI	09th April 2025
4	Submission of the initial version of design by PIs to ChipIN Centre as per guidelines of Design Tapeout Submission Form (i.e. Si Number, report on DRC clean, antenna check etc.)	02nd May 2025
5	ChipIN Centre to provide a Verification Report to PIs for initial version of designs submitted by PIs.	09th May 2025
6	PIs to submit the final version of fab-ready design/ GDS to ChipIN Centre addressing the issues, if any, highlighted in the Verification Report.	21st May 2025
7	Submission of designs of PIs by ChipIN Centre to SCL for fabrication.	31st May 2025
8	The designs to go in the fabrication lot at SCL Mohali	July 2025
9	Receiving of fabricated designs in packaged form by the PIs	31st March 2026

Design Tapeout Submission Process by Participating Institutions (PIs)

Step 1: Obtaining Silicon Number by PIs

1. The PIs to send an e-mail to ChipIN Centre to get the Silicon Number with duly filled Silicon_Number_Generation_Form (see attachment) by 4th April 2025. Please go through the Silicon_Numbering_Table (see attachment) for various code details to be used for filling it.
2. ChipIN Centre to provide Silicon number to the PI.

Step 2: Submission of Design

1. Participating Institutions (PIs) to provide their design details in the Design Tapeout Submission Form (DTSF) and Process Information Sheet (PIS sheet) for projects intended for tapeout at 180nm, SCL Mohali.
2. The DTSF provides information on various items, which must be considered when a design is submitted by PI to ChipIN Centre.
3. All the columns in the PIS sheet must be filled with the drop-in information, wherever provided. At places, where drop-in is not given, designer must write as per the column description only.

Design Tapeout Submission Form (DTSF) (see attachment)
Process Information Sheet (PIS sheet) (see attachment)

General Guidelines

1.0 Data Format and Communication:

1. Acceptable database format is GDSII only.
2. Complete database must be sent through e-mail to chipin@cdac.in. Do not provide any Google Drive link.
3. The communication has to be addressed through e-mail at:
   • To: chipin@cdac.in
   • CC: venkatark@cdac.in, viviand@cdac.in, support.c2s@meiy.gov.in
   ChipIN Centre,
   C2S Programme,
   C-DAC Bangalore, Opp. HAL Aeroengine Division,
   Old Madras Road, Byappanahalli,
   Bengaluru - 560 038.

2.0 Layout Grid

1. Minimum grid size used in the GDSII must be integer multiple of 0.005 µm.
2. Final GDSII window (including seal ring) must have Bottom left corner at (0,0) coordinate and the Top-Right corner coordinate must be rounded off to closest even number and it should be without any decimal places i.e., 10102 µm or 10100 µm for the case if coordinate comes at 10101.395 µm.

3.0 Design Kit

1. Do not rename cell names used in cell library.
2. Do not use library cell name for custom designed cells.
3. Do not edit standard cell library and I/O library.

4.0 Design Verification

1. The PIs to provide a clean GDSII database w.r.t. DRC, Density, and Antenna rules.
2. Before taping out the data, please provide checksum for GDSII file. Save the checksum value and byte count in a file, so that the same can be crosschecked at our end. e.g. cksum C2S0045_02052025_v1.gds 12345678 204 C2S0045_02052025_v1.gds
3. For GDSII integrity check while data transfer, MD5 checksum is must and need to be provided in addition to checksum so that the same can be crosschecked at our end. For calculating MD5, just open Linux terminal and type: md5sum ‘filename’ e.g. md5sum C2S0001_02052025_v1.gds
4. GDSII name and Top cell name format:
   • Format: silicon_no_date_version.gds (date format should be ddmmyyyy)
   • Top cell name should be "silicon number" only.
5. All the reports should be named as GDSII name. For instance:
   • siliconnum_date_version_drc.rpt
   • siliconnum_date_version_drc.summary
   • siliconnum_date_version_ant.rpt
6. All the columns in the Process Information Sheet (PIS sheet) must be filled with the drop-in information wherever provided. At places where drop-in is not given, designer must write as per the column description only.

5.0 Tapeout Checklist

#	Device Related Information	Yes/No
1	GDSII database provided
2	Silicon Number with PCI is mandatory. GDSII for this is included in the PDK. (Layer revision block may be placed if space permit)
3	Seal Ring with GND connection inserted?
4	Is DRC along with dummy fill Report clean?
5	Is Antenna along with dummy fill Report clean?
6	Dummy Fill done
7	Grid size 0.005µm used for layout
8	Whether Pads connected till top metal (TOP_M)?
9	Final Chip Origin should be at (0,0) after seal ring insertion.
10	Process Information Sheet duly filled?

6.0 Reports to be Included

1	Final DRC run Reports (Result database including density logs, summary, transcript, runset version)
2	Final Antenna Report (Result database, summary, transcript, runset version)
3	Devices type (or legal devices) used in layout report
4	Stream out log files
5	List of 3rd party IP used (If any with prior approval from SCL)
6	List of SCL IP used (If any with prior approval from SCL)
7	List of all legal layers used before silicon number insertion in Excel Format (Layer Name + layer number + datatype)
8	Coordinate of Silicon number
9	Process Information Sheet (Attached PIS Excel)

7.0 Tape-out and Packaging Related Checklist

#	Tape-out and Packaging Related Checklist	Please Tick / Specify
1	Mention the Die size including seal ring. Options supported: 2 x 2 mm², 3 x 3 mm², 4 x 4 mm², or 5 x 5 mm² (No other size is supported in the current tapeout under this program) For sizes greater than 5 x 5 mm² ChipIN will contact SCL’s PPG.	Specify 2 x 2 mm² or 3 x 3 mm² or 4 x 4 mm² or 5 x 5 mm²
2	The design should have a seal ring around it. The distance between chip boundary to seal ring should be a minimum of 10µm with DRC Clean.
3	The seal ring is connected to VSS (Ground).
4	No. of pins for Packaging the IC (Currently no. of pins should not be more than 100 for packaging).	Specify the No. of Pins
5	Package selected for packaging - Specify the Package Serial Number
6	The minimum pitch between two adjacent bond pads is 90µm for all bond pads.