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MPW Shuttle-IV

38 Designs submitted for Fabrication in MPW Manner at 180nm, SCL Mohali in Oct'2025 MPW Shuttle by ChipIN Centre
MPW SHUTTLE - IV TO SCL THROUGH CHIPIN CENTRE
Sl.No Silicon Number Institution Name Description of IC
FOUR-METAL PROCESS DESIGN SUBMISSIONS
1C2S0051VES Institute of Technology ChemburReconfigurable Analog to Digital converter (ADC)
2C2S0071IIITDM KancheepuramBinary Sleep Stage Classification: Distinguishing Wake from Sleep Using EEG
3C2S0072IIITDM KancheepuramAtrial Abnormality Detection system
4C2S0085IIT (ISM) DhanbadDigital ASIC chip is to interact with the OV7670 camera module in order to take images and perform simple digital image processing
5C2S0091NIT ROURKELAASCON authenticated encryption algorithm Hardware Implementation
6C2S0108IIT (ISM) DhanbadSpiking Nueral Network
7C2S0110PES UniversityDeep Learning Floating Point Unit (DL-FPU)
8C2S0111PES UniversityALU and FIR filters using Metaheuristic
9C2S0114PES UniversityAscon Cipher Encryption Block
10C2S0116PES Universityblock ciphers, Simon and the Tiny Encryption Algorithm (TEA) block ciphers implementation
11C2S0117PES UniversitySystolic Array Matrix Multiplier
12C2S0118PES UniversityFinite Impulse Response Filter using Metaheuristic
13C2S0121University of CalcuttaAir flow detector module in HVAC system
14C2S0126IIT HyderabadCMOS Image Sensors
15C2S0130NIT Durgapur32-bit Fully Digital Baseband Modulator system
16C2S0131NIT MeghalayaAnalog front-end system for Soil Moisture Detection
17C2S0134NIT PuducherrySingle Precision Floating point adder
18C2S0137VES Institute of Technology ChemburProgrammable Gain Amplifier
19C2S0138Indian Institute of Science BangaloreAnalog computation block
20C2S0140Indian Institute of Technology JammuRadiation-Hardened 4-kb 12T SRAM Array Using Switch Controlled Schmitt Trigger Bit-cell for Reliable Data Storage
21C2S0144Indian Institute of Technology IndoreRISC-V CPU (ECO RV)
22C2S0147Indian Institute of Technology IndoreBIO RV is a 32-bit Processor which is based on RISC-V Multicycle 32-bit Processor without pipeline
23C2S0148Indian Institute of Technology IndoreNeural Processing Engine
24C2S0158Indian Institute of Technology IndoreCORX: Performance-enhanced CORDIC-driven eXecution Engine
SIX-METAL PROCESS DESIGN SUBMISSIONS
25C2S0015Cambridge Institute of TechnologyBio-Potential Instrumentation Amplifier
26C2S0022Cambridge Institute of TechnologyQuad ALU
27C2S0086Model Engineering College, ThrikkakaraSAR ADC for high speed communication systems, medical imaging, radar systems and High-performance sensor interface
28C2S0129MNNIT AllahabadTransmitter
29C2S0132NIT SilcharAFE for Seizure Detection
30C2S0136NIT Arunachal PradeshDynamic Stress Management during NBTI
31C2S0141Indian Institute of Technology IndoreSRAM Memory Design
32C2S0143Indian Institute Technology IndorePHYSICAL UNCLONABLE FUNCTION FOR HARDWARE SECURITY
33C2S0146Indian Institute of Technology IndoreDigital Compute-in Memory
34C2S0149Indian Institute of Technology Indore8Kb SRAM Design
35C2S0150Indian Institute of Technology IndoreVECTOR MATRIX MULTIPLICATION(VMM)
36C2S0152Indian Institute of Technology Indore8Kb SRAM Compute-in-Memory
37C2S0156SGSITS indoreBattery Status Detector
38C2S0160IET DAVV, IndoreMemory Unit

Announcement for Tape-out submissions for MPW Shuttle-IV at 180nm, SCL Mohali through ChipIN Centre for Participating Institutions under C2S Programme for fabricating them in Oct’ 2025

1.0 ChipIN Centre (C-DAC Bangalore) is now accepting design tape-outs for MPW Shuttle-IV at 180nm, SCL Mohali, from Participating Institutions (PIs) under the C2S (Chips to Start-up) Programme for fabricating them in October 2025 as per following timelines.

# MPW Shuttle - IV Timelines
1 MPW Shuttle – IV Announcement by ChipIN Centre for fabrication of designs at 180nm, SCL Mohali by Participating Institutions (PI) 17th June 2025
2 PIs to submit request to ChipIN Centre for obtaining the Silicon number* from SCL. 27th June 2025
3 ChipIN Centre to provide Silicon number to the PI 04th July 2025
4 Submission of the initial version of design by the PIs to ChipIN Centre as per guidelines of Design Tapeout Submission Form (i.e. Si Number, report on DRC clean, antenna check etc.) 28th July 2025
5 ChipIN Centre to provide a Verification Report to PIs for initial version of designs submitted by PIs. 01st Aug 2025
6 PIs to submit the final version of fab-ready design/ GDS to ChipIN Centre addressing the issues, if any, highlighted in the Verification Report. 18th Aug 2025
7 Submission of designs of PIs by ChipIN Centre to SCL Mohali for fabrication. 31st Aug 2025
8 The designs to go in the fabrication lot at SCL Mohali Oct’ 2025
9 Receiving of fabricated designs in packaged form by the PIs 30th June 2026

Design Tapeout Submission Process by Participating Institutions (PIs)
Step 1: Obtaining Silicon Number by PIs
  1. The PIs to send an e-mail to ChipIN Centre to get the Silicon Number with duly filled Silicon_Number_Generation_Form (see attachment) by 27th June 2025. Please go through the Silicon_Numbering_Table (see attachment) for various code details to be used for filling it.
  2. ChipIN Centre to provide Silicon number to the PI.
Step 2: Submission of Design
  1. Participating Institutions (PIs) to provide their design details in the Design Tapeout Submission Form (DTSF) and Process Information Sheet (PIS sheet) for projects intended for tapeout at 180nm, SCL Mohali.
  2. The DTSF provides information on various items, which must be considered when a design is submitted by PI to ChipIN Centre.
  3. All the columns in the PIS sheet must be filled with the drop-in information, wherever provided. At places, where drop-in is not given, designer must write as per the column description only.

    4. Design Tapeout Submission Form (DTSF) (see attachment)
    Process Information Sheet (PIS sheet) (see attachment)
General Guidelines
1.0 Data Format and Communication:
  1. Acceptable database format is GDSII only.
  2. Complete database must be sent through e-mail to chipin@cdac.in. Do not provide any Google Drive link.
  3. The communication has to be addressed through e-mail at: ChipIN Centre,
    C2S Programme,
    C-DAC Bangalore, Opp. HAL Aeroengine Division,
    Old Madras Road, Byappanahalli,
    Bengaluru - 560 038.
2.0 Layout Grid
  1. Minimum grid size used in the GDSII must be integer multiple of 0.005 µm.
  2. Final GDSII window (including seal ring) must have Bottom left corner at (0,0) coordinate and the Top-Right corner coordinate must be rounded off to closest even number and it should be without any decimal places i.e., 10102 µm or 10100 µm for the case if coordinate comes at 10101.395 µm.
3.0 Design Kit
  1. Do not rename cell names used in cell library.
  2. Do not use library cell name for custom designed cells.
  3. Do not edit standard cell library and I/O library.
4.0 Design Verification
  1. The PIs to provide a clean GDSII database w.r.t. DRC, Density, and Antenna rules.
  2. Before taping out the data, please provide checksum for GDSII file. Save the checksum value and byte count in a file, so that the same can be crosschecked at our end. e.g. cksum C2S0001_01062025_v1.gds 12345678 204 C2S0001_01062025_v1.gds
  3. For GDSII integrity check while data transfer, MD5 checksum is must and need to be provided in addition to checksum so that the same can be crosschecked at our end. For calculating MD5, just open Linux terminal and type: md5sum ‘filename’ e.g. md5sum C2S0001_01062025_v1.gds
  4. GDSII name and Top cell name format:
    • Format: silicon_no_date_version.gds (date format should be ddmmyyyy)
    • Top cell name should be "silicon number" only.
  5. All the reports should be named as GDSII name. For instance:
    • siliconnum_date_version_drc.rpt
    • siliconnum_date_version_drc.summary
    • siliconnum_date_version_ant.rpt
  6. All the columns in the Process Information Sheet (PIS sheet) must be filled with the drop-in information wherever provided. At places where drop-in is not given, designer must write as per the column description only.

5.0 Tapeout Checklist
# Device Related Information Yes/No
1 GDSII database provided
2 Silicon Number with PCI is mandatory. GDSII for this is included in the PDK. (Layer revision block may be placed if space permit)
3 Seal Ring with GND connection inserted?
4 Is DRC along with dummy fill Report clean?
5 Is Antenna along with dummy fill Report clean?
6 Dummy Fill done
7 Grid size 0.005µm used for layout
8 Whether Pads connected till top metal (TOP_M)?
9 Final Chip Origin should be at (0,0) after seal ring insertion.
10 Process Information Sheet duly filled?

6.0 Reports to be Included
1 Final DRC run Reports (Result database including density logs, summary, transcript, runset version)
2 Final Antenna Report (Result database, summary, transcript, runset version)
3 Devices type (or legal devices) used in layout report
4 Stream out log files
5 List of 3rd party IP used (If any with prior approval from SCL)
6 List of SCL IP used (If any with prior approval from SCL)
7 List of all legal layers used before silicon number insertion in Excel Format (Layer Name + layer number + datatype)
8 Coordinate of Silicon number
9 Process Information Sheet (Attached PIS Excel)

7.0 Tape-out and Packaging Related Checklist
# Tape-out and Packaging Related Checklist Please Tick / Specify
1 Mention the Die size including seal ring. Options supported: 2 x 2 mm², 3 x 3 mm², 4 x 4 mm², or 5 x 5 mm²
(No other size is supported in the current tapeout under this program)
For sizes greater than 5 x 5 mm² ChipIN will contact SCL’s PPG.		 Specify 2 x 2 mm² or 3 x 3 mm² or 4 x 4 mm² or 5 x 5 mm²
2 The design should have a seal ring around it. The distance between chip boundary to seal ring should be a minimum of 10µm with DRC Clean.
3 The seal ring is connected to VSS (Ground).
4 No. of pins for Packaging the IC
(Currently no. of pins should not be more than 100 for packaging).		 Specify the No. of Pins
5 Package selected for packaging (Refer Serial No. 8) - Specify the Package Serial Number
6 The minimum pitch between two adjacent bond pads is 90µm for all bond pads.

8.0 Preferred Die Size and plastic packages (Chip-on-Board Packaging Options)
Serial No. Die Size (mm) Package Size (mm) Pin Count Package Lead Pitch (mm) CoB Package Type
12.0 x 2.07.0 x 7.0161.0QFN
23.0 x 3.07.0 x 7.0161.0QFN
32.0 x 2.08.4 x 8.4241.0QFN
43.0 x 3.08.4 x 8.4241.0QFN
53.0 x 3.09.0 x 9.0281.0QFN
62.0 x 2.010.0 x 10.0321.0QFN
73.0 x 3.010.0 x 10.0321.0QFN
82.0 x 2.014.0 x 14.0481.0QFN
93.0 x 3.014.0 x 14.0481.0QFN
102.0 x 2.018.0 x 18.0641.0QFN
113.0 x 3.018.0 x 18.0641.0QFN
124.0 x 4.014.0 x 14.0481.0QFN
135.0 x 5.014.0 x 14.0481.0QFN
144.0 x 4.018.0 x 18.0641.0QFN
155.0 x 5.018.0 x 18.0641.0QFN
164.0 x 4.010.0 x10.0721.0QFN
175.0 x 5.020.0 x 20.0721.0QFN
184.0 x 4.020.0 x 20.0801.0QFN
195.0 x 5.020.0 x 20.0801.0QFN
204.0 x 4.025.0 x 25.0881.0QFN
215.0 x 5.025.0 x 25.0881.0QFN
224.0 x 4.028.0 x 28.01001.0QFN
235.0 x 5.028.0 x 28.01001.0QFN

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