Resources under C2S Programme
- Centralized Electronic Design Automation
(EDA) tools facility
- Access of EDA tools facility to all Participating
Institutions in centralize manner for designing of
- Enablement of optimal utilization of licenses required by
Participating Institutions for development of their designs.
- Instruction Enhancement Programmes (IEPs)
- IEPs would be organized on Emerging Technology area and
VLSI/Embedded System design.
- Industry experts and Experts from EDA tool vendors etc.
would be invited for providing technical sessions.
- Recorded technical sessions of the IEPs would also be made
available at C2S website.
- Skilled Manpower Advanced Research and
Training (SMART) facility
- SMART lab facility, set up at NIELIT Calicut, is a
national facility for Remote VLSI and Embedded System advanced
- Targeted to facilitate electronics hardware design
technology and training needs for small scale electronics
industries, researchers, and students across the country.
- Students, Researchers, Startup industries will be able to
access the facility, anytime and anywhere.
- Enablement of remote hardware access to approximately
- Generation of skilled manpower as well as, Intellectual
Property generation in VLSI, electronics hardware and embedded
system design areas.
- Under the programme, annual Conference/Workshop/Symposium
etc. with emphasis on emerging areas/trends in
Microelectronics/VLSI/Embedded System design/Hardware Security
would be organized.
- Leading National/International Experts/guest faculty from
Academia/R&D organizations/Industry would be invited to deliver
lectures in these workshops /symposiums/webinars.
- Students/Researchers would be supported to attend and
present the paper in International Conferences for the work
carried out under the projects.
- Chip Design Infrastructure
- Providing FPGA boards for early prototyping and embedded
software development based on requirements.
- Fab compliance validation of designs, design flow
establishment with a specific set of EDA tools and Fab PDK,
Packaging of Chips, Testing and Characterization would be provided
in centralized manner through India Chip Centre.
- Handholding the new Institutions/Startups participating
under the Programme for their ASIC and FPGA based designs.
- Providing Compute Infrastructure for simulating designs
based on requirements.
- Workstations/Servers for 8 North eastern NITs.
- Creation of reusable IPs repository
- Repository of designs carried out by the participating
Institutions under the program would be set up at Chip Centre.
- Repository of Reusable IP cores could be made readily
available for use by other designers/Participating Institutes.
- Protection of Intellectual Property (IPs) Core Generated
- To protect the IP generated, Institutions would be
encouraged to file Patents, protect ASICs/IP Core (under
Semiconductor Integrated Circuits Layout-Design Circuits Layout
Design Act) etc. developed under the Projects.
- Fund Provision would be kept for filing of Patents of the
IP Core(s) generated.
- India Chip Programme
- Fabrication at Overseas foundry on need basis in Multi
Project Wafer (MPW) mode.
- This will include ASICs designed by the
students/researchers of Academia/R&D Institutions/Startup/MSMEs
participating under C2S Programme.
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