No. of Training Sessions organized by ChipIN Centre under C2S Programme - 2024
# | TOPIC | SESSION | ORGANIZER / CONDUCTED BY | DATE | MODE OF CONDUCTION | SESSION RECORDINGS |
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1 | Interactive Session on Latest Shared PDK Related Doubts Clarification by SCL Chandigarh | The session provided participants with the opportunity to ask questions related to the latest shared SCL PDK. The session focused on the enablement of the SCL 180nm PDK with EDA tools. | ChipIN / SCL | 18-April-2024 | (Online) Session | Technical Interactive Session on SCL PDK |
2 | Technical Session on SCL 180nm PDK and its Integration into the Design Flow | During this technical session experts from SCL team addressed C2S participants queries related to SCL PDK. The session also focused on integration of the SCL PDK with the design flow. | ChipIN / SCL | 03-June-2024 | (Online) Session | Technical Session on SCL 180nm PDK and its Integration into Design Flow |
3 |
Technical session on SCL 180nm PDK |
This technical session, will cover introduction to SCL PDK, Overview of Standard cells and IO cells from SCL used in Digital design., technical details and usage of Tech, LIB, and LEF files for standard and IO cells in the PDK within the digital design flow, technical details about map files, their usage, and importance, Physical verification (DRC, Antenna, LVS, PeX, etc.) with SCL PDK, Comprehensive overview of the Digital design flow with SCL PDK, Tapeout requirements for a Digital design with SCL PDK etc. |
ChipIN / SCL | 03-July-2024 | (Online) Session | Technical Session on SCL 180nm PDK for Digital Design Flow |
4 | Technical Sessions by SCL on ASIC Design (Analog and Mixed Signal), Packaging & Testing related design issues, and SCL Foundry Process - Day 1 |
The Session will cover Analog and Mixed Signal ASIC Design Flow with SCL 180nm PDK and Packaging & Testing related design issues |
ChipIN / SCL | 8-August-2024 | (Online) Session | Technical Sessions by SCL on ASIC Design (Analog and Mixed Signal), Packaging & Testing related design issues |
5 | Technical Sessions by SCL on ASIC Design (Analog and Mixed Signal), Packaging & Testing related design issues, and SCL Foundry Process - Day 2 |
The Session will cover SCL Foundry Process Features and Capabilities |
ChipIN / SCL | 9-August-2024 | (Online) Session | Technical (Online) Session on SCL Foundry Process Features and Capabilities |
6 | Technical (Online) Session on SCL's 180nm technology process (both 4-metal and 6-metal) by SCL Chandigarh |
The Session would cover the following topics:
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ChipIN / SCL | 10-September-2024 | (Online) Session | Technical (Online) Session on SCL's 180nm technology process (both 4-metal and 6-metal) |
7 | Online Session on SCL 180nm Tapeout Process (November Shuttle) by SCL Chandigarh |
The Session willl discuss the process for filling out the "Silicon Number Generation Form" Understanding the all columns of the "Silicon Numbering Table" Completing all sections of "Process Information Sheet" for SCL 180nm, Detailed guidance on the tapeout submission form, including: General Guidelines for filling out the form, Layout Grid options, Instructions for "Process details" section, tapeout checklist, Reports to be included with design submissions tapeout and packaging guidelines. |
ChipIN / SCL | 27-September-2024 | (Online) Session | Online Session on SCL 180nm (November) Shuttle Tapeout Process by SCL Chandigarh |
8 | Technical (Online) Session on SCL's 180nm foundry requirements with an example/sample design for the tapeout |
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ChipIN / SCL | 16-October-2024 | (Online) Session | Technical (Online) Session on SCL's 180nm Foundry Design Tapeout Sign-off Requirements for Design Submissions |
9 | Technical (Online) Session on SCL's Chip-on-Board (CoB) packaging options offered for C2S participating institutions targeting SCL 180nm |
The session would cover the following CoB packaging details:
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ChipIN / SCL | 12-November-2024 | (Online) Session | Technical (Online) Session on SCL's Chip-on-Board (CoB) packaging options offered for C2S participating institute |
# | TOPIC | SESSION | ORGANIZER / CONDUCTED BY | DATE | MODE OF CONDUCTION | SESSION RECORDINGS |
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1 | Technical (Online) Sessions on Custom Analog Design Flow using Cadence Virtuoso by ChipIN | Day 1: Schematic entry and Spectre Analysis | ChipIN | 05-Apr-24 | (Online) Session | Schematic entry and Spectre Analysis |
2 | Day 2: Custom Layout Design, Verification and Post-Layout Analysis | ChipIN | 16-Apr-24 | (Online) Session | Custom Layout Design Verification and Post_Layout Analysis | |
3 | Day 1: Technical (Online) Sessions on Front End Design Flow by ChipIN Team | RTL Coding, Async. FIFO Design, Simulation | ChipIN | 03-May-24 | (Online) Session | Day_1 Technical (Online) Sessions on Front End Design Flow by ChipIN Team |
4 | Day 2: Technical (Online) Sessions on Front End Design Flow by ChipIN Team | Linting using Cadence Jasper Gold | ChipIN | 06-May-24 | (Online) Session | Day_2 Technical (Online) Sessions on Front End Design Flow by ChipIN Team |
5 | Day 3: Technical (Online) Sessions on Front End Design Flow by ChipIN Team | CDC & RDC using Cadence Jasper Gold | ChipIN | 07-May-24 | (Online) Session | Day_3 Technical (Online) Sessions on Front End Design Flow by ChipIN Team |
6 | Day 4: Technical (Online) Sessions on Front End Design Flow by ChipIN Team | X-propagation using Cadence Jasper Gold | ChipIN | 08-May-24 | (Online) Session | Day_4 Technical (Online) Sessions on Front End Design Flow by ChipIN Team |
7 | Technical (Online) Sessions on Synthesis and Post Synthesis Flow by ChipIN Team | Writing/Defining timing constraints for Async. FIFO Design, TCL scripting for Synthesis, and Genus Synthesis Tool Flow | ChipIN | 06-Jun-24 | (Online) Session | Day 1 Technical (Online) Sessions on Synthesis and Post Synthesis Flow by ChipIN Team |
8 | Logic Equivalence Check, post synthesis simulations, zero delay simulation, unit delay simulation and sdf simulations using Xcelium Tool | ChipIN | 07-Jun-24 | (Online) Session | Day 2 Technical (Online) Sessions on Synthesis and Post Synthesis Flow by ChipIN Team | |
9 | Technical (Online) Sessions on Physical Design Flow by ChipIN Team | Start of Physical Design: Import, Floorplan, IO fillers, and Power plan, creation of IO assignment file, MMMC file (GUI + Script) using Innovus Tool | ChipIN | 19-Jun-24 | (Online) Session | Day 1 Technical (Online) Sessions on Physical Design Flow by ChipIN Team |
10 | Placement, Clock Tree Synthesis and STA: Placement, Creation of Clock tree spec file, CTS (Cluster, trial and full mode) and ECO to fix STA if any etc. | ChipIN | 20-Jun-24 | (Online) Session | Day 2 Technical (Online) Sessions on Physical Design Flow by ChipIN Team | |
11 | Routing, std. cell fillers and Sign-off, ECO post route and sign-off, Post Route netlist simulations, zero delay simulation, unit delay simulation, back annotation with sdf | ChipIN | 21-Jun-24 | (Online) Session | Day 3 Technical (Online) Sessions on Physical Design Flow by ChipIN Team | |
12 | Online Session on Installing the Latest Shared SCL PDK by ChipIN Team | Doubts and queries session related to SCL PDK installation | ChipIN | 21-Jun-24 | (Online) Session | Online Session on Installing the Latest Shared SCL PDK by ChipIN Team |
13 | Technical (Online) Sessions on Physical Design Flow by ChipIN Team | LEC check for post route netlist, Gate Level Simulation for Post Route netlist such as zero delay simulation, unit delay simulation, sdf simulation(back annotation) etc. | ChipIN | 15-Jul-24 | (Online) Session | Day 1 Technical (Online) Sessions on Physical Design Flow by ChipIN Team |
14 | Technical (Online) Sessions on Physical Design Flow by ChipIN Team | Standard cells, io cells, fifo GDS-II stream in Virtuoso, silicon number insertion and seal-ring placement etc. | ChipIN | 16-Jul-24 | (Online) Session | Day 2 Technical (Online) Sessions on Physical Design Flow by ChipIN Team |
15 | Online Interactive Session on Implementing Unique Host-ID(s) for Effective EDA Tool Usage under C2S Programme | Procedure for changing the hostname in linux system, FAQ's & guidelines related to unique Host-ID(s) implementation etc. | ChipIN | 06-Sep-24 | (Online) Session | Online Interactive Session on Implementing Unique Host-ID(s) for Effective EDA Tool Usage under C2S Programme |
16 | Technical (Online) Sessions on Physical Design Flow by ChipIN Team | Block level DRC, Dummy Fill, Chip level DRC, Antenna DRC and LVS etc. | ChipIN | 17-Sep-24 | (Online) Session | Technical (Online) Sessions on Physical Design Flow by ChipIN Team |
17 | Technical (Online) Sessions on Physical Design Flow by ChipIN Team | Timing check with Tempus, using sdf generated from Innovus as well as from Virtuoso | ChipIN | 20-Sep-24 | (Online) Session | Day 1 Technical (Online) Sessions on Physical Design Flow by ChipIN Team |
18 | Pex extraction and Spice simulations using spectre/unisim and tapeout to SCL foundry | ChipIN | 23-Sep-24 | (Online) Session | Day 2 Technical (Online) Sessions on Physical Design Flow by ChipIN Team |
# | TOPIC | SESSION DETAILS | PRESENTER | DATE | NO. OF ATTENDEES | FEEDBACK |
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1 | Interactive Technical Session on Siemens QuestaSim EDA Tool |
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CoreEL / Siemens EDA | 17-Jan-2024 | 100 | |
2 | Online session by ChipIN team on EDA Tools installation, Port mapping, License Checkout and IP Whitelisting issues - Reg. | To help C2S institutes who are still encountering challenges while installing EDA tools, accessing centralized licenses, configuring environment variables, etc. | ChipIN | 18-Jan-2024 | 24 | |
3 | Interactive Technical Session on Siemens Questa EDA Tool |
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CoreEL / Siemens EDA | 25-Jan-2024 | 92 | |
4 | Interactive Technical Session on Siemens Questa CoverCheck and CDC |
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CoreEL / Siemens EDA | 30-Jan-2024 | 45 | |
5 | A Preliminary Getting Started online session by Cadence | Installing the Cadence EDA tools, accessing centrally hosted EDA licenses, setting up environment variables, support related, etc. | Entuple / Cadence | 31-Jan-2024 | 92 | |
6 | A Preliminary Getting Started online session by Siemens-EDA | Installing the Siemens EDA tools, accessing centrally hosted EDA licenses, setting up environment variables, support related, etc. | CoreEL / Siemens EDA | 1-Feb-2024 | 42 | |
7 | A Preliminary Getting Started online session by Synopsys | Installing the Synopsys EDA tools, accessing centrally hosted EDA licenses, setting up environment variables, support related, etc. | Synopsys | 1-Feb-2024 | 61 | |
8 | IEP on ASIC Digital Design Using 180nm PDK | Insights into RTL-to-GDSII using Cadence EDA Tools for Digital IC design with a focus on 180nm PDK | ChipIN | 12-Feb-2024 to 16-Feb-2024 |
83 | |
9 | Online session by ChipIN team on EDA Tools installation, Port mapping, License Checkout and IP Whitelisting issues - Reg. | To help C2S institutes who are still encountering challenges while installing EDA tools, accessing centralized licenses, configuring environment variables, etc. | ChipIN | 22-Feb-2024 | 63 | |
10 | Four-day Technical Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx | FPGA 7-Series Architecture (4-hour session + 1-hour discussion/doubt clearance) | CoreEL / Xilinx (AMD) | 5-Mar-2024 | 224 | |
11 | Four-day Technical Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx | Vivado Flow (4-hour session + 1-hour discussion/doubt clearance) | CoreEL / Xilinx (AMD) | 6-Mar-2024 | 190 | |
12 | Four-day Technical Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx | Hardware Debugging (4-hour session + 1-hour discussion/doubt clearance) | CoreEL / Xilinx (AMD) | 11-Mar-2024 | 100 | |
13 | Four-day Technical Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx | Exploring Interfacing with Soft Core Processor (5.5-hour session) | CoreEL / Xilinx (AMD) | 12-Mar-2024 | 120 | |
14 | Online interactive session by CoreEl/Siemens team on the ODT Usage - Reg. |
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CoreEL / Siemens EDA | 22-Mar-2024 | 57 | |
15 | Interactive session with Synopsys regarding EDA Tool installation and License checkout | Installing the Synopsys EDA tools, accessing centrally hosted EDA licenses, setting up environment variables etc. | Synopsys | 27-Mar-2024 | 61 | |
16 | Technical (Online) Sessions on Custom Analog Design Flow using Cadence Virtuoso by ChipIN |
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ChipIN |
05-Apr-2024 16-Apr-2024 19-Apr-2024 22-Apr-2024 |
Day 1 - 471 Day 2 - 72 Day 3 - 103 Day 4 - 136 |
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17 | Five-day Technical (Online) Sessions on RTL Design and Verification by Synopsys |
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Synopsys | 03-Apr-2024 04-Apr-2024 10-Apr-2024 24-Apr-2024 25-Apr-2024 |
Day 1 - 371 Day 2 - 226 Day 3 - 150 Day 4 - 107 Day 5 - 76 |
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18 | Two-Day Technical (Online) Sessions on RedHawk-SC EDA Tool by Ansys |
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Ansys | 08-Apr-2024 & 15-Apr-2024 |
Day 1 - 75 Day 2 - 33 |
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19 | Interactive (Online) Session on latest shared PDK related doubts clarfication by SCL Chandigarh |
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ChipIN / SCL | 18-Apr-2024 | 118 | |
20 | Online session by ChipIN team on EDA Tools installation, Port mapping, License Checkout and IP Whitelisting issues | To help C2S institutes who are still encountering challenges while installing EDA tools, accessing centralized licenses, configuring environment variables, etc. | ChipIN | 23-Apr-2024 | 33 | |
21 | Two-Day Technical (Online) Sessions on Tessent EDA Tool by Siemens |
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CoreEL / Siemens EDA | 29-Apr-2024 30-Apr-2024 |
Day1 - 119 Day2 - 63 | |
22 | A Preliminary Getting Started Online Session by Keysight |
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Keysight | 30-Apr-2024 | 68 | |
23 | Fundamentals of Power-Efficient Microprocessor Design by Dr. Hofstee (IBM) |
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IBM | 2-May-2024 | 123 | |
24 | Technical (Online) Sessions on Front End Design Flow by ChipIN Team |
DAY 1 :
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ChipIN | 03-May-2024 | 76 | |
DAY 2 :
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ChipIN | 06-May-2024 | 106 | |||
DAY 3 :
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ChipIN | 07-May-2024 | 83 | |||
DAY 4 :
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ChipIN | 08-May-2024 | 76 | |||
25 | Technical (Online) Sessions on SMART LAB by NIELET Calicut | Available facilities in the SMART Lab, Course details, SMART Lab Demonstration (VLSI/Embedded) and Upcoming courses | NIELET Calicut | 07-May-2024 | 33 | |
26 | Two Day Interactive (Online) Sessions on Siemens Calibre EDA Tool |
Introduction to Calibre EDA Tool, DRC Setup and Rule Violations check etc. |
CoreEL / Siemens EDA | 09-May-2024 | 77 | |
CoreEL / Siemens EDA | 10-May-2024 | 71 | ||||
27 | Technical (Online) Session on Keysight Cliosoft Software (Design Data Management tool) |
Importance of Design Data Management (DDM), Introduction to Cliosoft's revolutionary solutions, SOS's Simple Solutions to Big Problems, Data Security, Network Storage Optimization, Design and IP Reuse, Live Demo and Case Studies etc. |
Keysight | 13-May-2024 | 31 |
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28 | Technical (Online) Session on Full-Custom and Semi Custom IC Design Flow by Entuple Team | Day 1: Introduction to Full Custom IC Design Flow and Cadence Solutions, Design Specification and Circuit Analysis, Schematic Capture, Symbol Creation and Testbench preparation, Functional Simulation and Parameter Analysis, Layout Design, Parasitic Extraction, Physical Verification, Post Layout Simulation, SPICE Simulation etc | Entuple / Cadence | 14-May-2024 |
123 |
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Day 2: Introduction to Semi-Custom IC Design Flow and Cadence Solutions, Design specifications and RTL Coding, Testbench, creation and Functional Simulation, Formal Verification and Code Coverage Analysis, SDC Preparation, RTL Synthesis, and Reports Analysis, Synthesis with DFT, Logic Equivalence Check, Physical Implementation Floor Planning, Timing and Power Analysis, Gate Level Simulation etc. | Entuple / Cadence | 15-May-2024 | 117 |
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29 | Four-day Technical Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx (Phase 2) | Day 1:Introduction to AMD-Xilinx FPGA-FPGA Design Flow, Overview of AMD-Xilinx FPGA and SoC families and architectures Introduction to Zynq SoC Architecture etc.(4-hour session) | CoreEL Technologies | 16-May-2024 | 216 |
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Day 2:Creation of AXI Based Custom IP, Software and Hardware Debugging, Debugging Using Hardware Analyzer etc. (IP-XACT) (4-hour session) | CoreEL Technologies | 17-May-2024 | 135 |
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Day 3:Introduction to Zynq SoC Direct Memory Access Controller, Working with PMODs, Implement the Hardware using Vivado Design Suite, Export Hardware and Develop an application code to view output using UART protocol etc. | CoreEL Technologies | 20-May-2024 | 96 |
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Day-4:Introduction to the PYNQ project, Pynq Z2 Board setup, Getting started with Jupyter Notebooks, Getting started with IPython, Exploring the board Programming on board peripherals etc. | CoreEL Technologies | 21-May-2024 | 136 |
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30 | Online session by ChipIN team on EDA Tools installation, Port mapping, License Checkout and IP Whitelisting issues - Reg. | To help C2S institutes who are still encountering challenges while installing EDA tools, accessing centralized licenses, configuring environment variables, etc. | ChipIN | 22-May-2024 | 33 |
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31 | Five-Day Technical (Online) Workshop on Physical Design by Synopsys | Day 1:ASIC flow and Synthesis | Synopsys | 27-May-2024 | 211 |
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Day 2: Input files and Floorplan | Synopsys | 28-May-2024 | 171 |
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Day 3: Placement, Power plan, CTS | Synopsys | 29-May-2024 | 125 |
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Day 4: Routing and checks after routing | Synopsys | 30-May-2024 | 115 |
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Day 5: STA, DFM and Output files | Synopsys | 31-May-2024 | 102 |
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32 | Technical (Online) session on SCL 180nm PDK and its integration into the design flow. |
During this technical session, participants will have the opportunity to clarify their doubts and queries related to SCL PDK. |
ChipIN / SCL | 03-June-2024 | 134 |
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33 | Technical (Online) Session on accessing and using Xilinx Alveo U 55C and VCK5000 Versal FPGA Boards. |
Introduction to Xilinx Platforms, Intro to Vitis for Acceleration Platforms, Vitis Tool Flow, Vitis Design Analysis, Alveo U55C High Performance Compute Card, VCK5000 Versal Development Card etc. |
CoreEL / Xilinx | 04-June-2024 | 89 |
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34 | Technical (Online) Session on Introduction to Keysight ADS and Schematic Software |
Introductory session on Keysight ADS and Schematic EDA Software. |
Keysight | 05-June-2024 | 47 |
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35 | Technical (Online) Sessions on Synthesis and Post Synthesis Flow by ChipIN Team |
Writing/Defining timing constraints for Async. FIFO Design, TCL scripting for Synthesis, and Genus Synthesis Tool Flow |
ChipIN Team | 06-June-2024 | 72 |
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Logic Equivalence Check, post synthesis simulations, zero delay simulation, unit delay simulation and sdf simulations using Xcelium Tool |
ChipIN Team | 07-June-2024 | 40 |
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36 | Technical Session on Questa simulator and Linting - Day 1 |
Questa Sim Introduction (Features and Flows), Questa Sim usage in GUI, Command line and in-built examples demo, Questa Sim Advanced features discussion, Advanced GUI -Coverage, Debug etc. |
Siemens EDA | 10-June-2024 | 47 |
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37 | Technical Session Questa simulator and Linting - Day 2 |
Introduction to Questa Design solutions and Introduction to Linting, Questa Lint, Methodologies and goals, Advanced Features, Demo and Graphical user interface, Queries etc. |
Siemens EDA | 11-June-2024 | 28 |
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38 | Ansys Technical Session on Totem EDA Tool |
The session will cover Totem Platform Overview, Totem Static Analysis, Totem Dynamic Analysis, Analysis, IP Model Creation, GUI Wizard etc. |
M/s Ansys | 13-June-2024 | 36 |
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39 | Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 1 |
The Session Covers the Start of Physical Design: Import, Floorplan, IO fillers, and Power plan, creation of IO assignment file, MMMC file (GUI + Script) using Innovus Tool |
ChipIN Team | 19-June-2024 | 71 |
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40 | Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 2 |
The session covers the Placement, Clock Tree Synthesis and STA: Placement, Creation of Clock tree spec file, CTS (Cluster, trial and full mode) and ECO to fix STA if any |
ChipIN Team | 20-June-2024 | 68 |
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41 | Online Session on Installing the Latest Shared SCL PDK by ChipIN Team |
During this technical session, participants will have the opportunity to clarify their doubts and queries related to SCL PDK installation. |
ChipIN Team | 21-June-2024 (11:30am to 12:30pm) | 65 |
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42 | Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 3 |
The session will cover the Routing, std. cell fillers and Sign-off, ECO post route and sign-off, Post Route netlist simulations, zero delay simulation, unit delay simulation, back annotation with sdf |
ChipIN Team | 21-June-2024 (2:30pm to 5:30pm) | 49 |
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43 | Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 1 |
The session will cover Custom Compiler Overview, Library Manager, Schematic Editor, Symbol Creation etc. |
Synopsys | 24-June-2024 | 157 |
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44 | Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 2 |
The session will cover PrimeWave Design Environment and Simulation etc. |
Synopsys | 25-June-2024 | 121 |
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45 | Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 3 |
The session will cover PrimeSim Continuum |
Synopsys | 26-June-2024 | 92 |
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46 | Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 4 |
The session will cover Layout Editor, SDL. |
Synopsys | 27-June-2024 | 78 |
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47 | Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 5 |
The session will cover Physical Verification and Parasitic Extraction |
Synopsys | 28-June-2024 | 71 |
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48 | Technical (Online) session on SCL 180nm PDK |
This technical session, will cover introduction to SCL PDK, Overview of Standard cells and IO cells from SCL used in Digital design., technical details and usage of Tech, LIB, and LEF files for standard and IO cells in the PDK within the digital design flow, technical details about map files, their usage, and importance, Physical verification (DRC, Antenna, LVS, PeX, etc.) with SCL PDK, Comprehensive overview of the Digital design flow with SCL PDK, Tapeout requirements for a Digital design with SCL PDK etc. |
SCL Chandigarh | 03-July-2024 | 122 |
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49 | Technical (Online) Session on Keysight ADS HDS Software |
Technical session on Keysight ADS HSD-High Speed Simulation: Signal Integrity, Power Integrity, Memory Design |
M/s. Keysight Technologies Pvt. Ltd | 04-July-2024 | 52 |
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50 | Technical (Online) Session on Ansys PowerArtist EDA Tool |
Introduction to PowerArtist, Steps to Power-Efficient RTL Design, Power Computation Fundamentals; PowerArtist Setup and Flow, RTL Import - "Elaborate", Perform Architectural Trade-Offs (Explore Power of Micro-Architectures); Static Power Efficiency Audit - "AnalyzeStaticEfficiency", Profile Real Application Scenarios (Vector Analysis and Power Profiling), Check Power versus Budget Early (Average and Time-Based Power Analysis), Visually Debug Power for Anomalies, Reduce Power using RTL Techniques etc. |
Ansys Team | 09-July-2024 | 89 |
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51 | Embedded for Beginners |
Session Details [Click Here] |
NIELIT | 10-July-2024 |
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52 | VLSI for Beginners |
Session Details [Click Here] |
NIELIT | 10-July-2024 |
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53 | Python for Beginners |
Session Details [Click Here] |
NIELIT | 10-July-2024 |
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54 | Introduction to MATLAB & Simulink |
Session Details [Click Here] |
NIELIT | 10-July-2024 |
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55 | Machine Learning using Python |
Session Details [Click Here] |
NIELIT | 10-July-2024 |
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56 | Online interactive session on EDA Tools installation |
The session would be covering issues related to installing the Synopsys EDA tools, accessing centrally hosted EDA licenses, setting up environment variables, support related, etc. |
Synopsys Team | 11-July-2024 | 141 |
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57 | MicroPython for Beginners |
Session Details [Click Here] |
NIELIT | 17-July-2024 |
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58 | Technical (Online) Session on Cadence Innovus EDA Tool |
Introduction to Semi-Custom IC Design Flow (RTL-GDSII), Physical Design process and tool flow, Data interpretation for Physical Design, Physical design flow for Block and Chip level etc. Physical Implementation using Innovus that includes, Floor Planning, Power Planning, Placement, CTS, Routing, Timing and Power Analysis, Physical Verification etc. |
Entuple Team | 12-July-2024 | 92 |
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59 | Technical (Online) Session on Physical Design Tool flow - Day 1 |
The session will cover LEC check for synthesis netlist with post route netlist, Post Route netlist simulations, zero delay simulation, unit delay simulation, back annotation with sdf |
ChipIN Team | 15-July-2024 | 62 |
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60 | Technical (Online) Session on Physical Design Tool flow - Day 2 |
The session will cover std. cells, io cells, fifo GDS-II stream in Virtuoso, silicon number insertion and seal-ring placement etc. |
ChipIN Team | 16-July-2024 | 42 |
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61 | Online interactive session on Xilinx EDA Tools installation by CoreEL Team |
The session would be covering overview of EDA Tools from AMD-Xilinx, Tool installation procedure, License acquisition procedure, frequently encountered issues, and solutions etc. |
CoreEL Team | 18-July-2024 | 44 |
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62 | Technical (Online) Session on RTL to GDS Flow - Day 1 |
RTL to GDS Flow |
Synopsys Team | 22-July-2024 | 390 |
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63 | Technical (Online) Session on RTL to GDS Flow - Day 2 |
RTL to GDS Flow |
Synopsys Team | 23-July-2024 | 274 |
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64 | Technical (Online) Session on RTL to GDS Flow - Day 3 |
RTL to GDS Flow |
Synopsys Team | 24-July-2024 | 216 |
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65 | Technical (Online) Session on RTL to GDS Flow - Day 4 |
RTL to GDS Flow |
Synopsys Team | 25-July-2024 | 174 |
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66 | Technical (Online) Session on RTL to GDS Flow - Day 5 |
RTL to GDS Flow |
Synopsys Team | 26-July-2024 | 148 |
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67 | Embedded for Beginners |
Session Details [Click Here] |
NIELIT | 10-August-2024 |
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68 | VLSI for Beginners |
Session Details [Click Here] |
NIELIT | 10-August-2024 |
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69 | Python for Beginners |
Session Details [Click Here] |
NIELIT | 10-August-2024 |
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70 | Introduction to MATLAB & Simulink |
Session Details [Click Here] |
NIELIT | 10-August-2024 |
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71 | MicroPython for Beginners |
Session Details [Click Here] |
NIELIT | 21-August-2024 |
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72 | RISC-V programming primer |
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NIELIT | - | ||
73 | Machine Learning using Python |
Session Details [Click Here] |
NIELIT | 10-August-2024 |
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74 | Data Analysis Using Python |
Session Details [Click Here] |
NIELIT | 21-August-2024 |
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75 | Technical Sessions by SCL on ASIC Design (Analog and Mixed Signal), Packaging & Testing related design issues, and SCL Foundry Process - Day 1 |
The Session will cover Analog and Mixed Signal ASIC Design Flow with SCL 180nm PDK and Packaging & Testing related design issues |
SCL Team | 8-August-2024 | 272 |
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76 | Technical Sessions by SCL on ASIC Design (Analog and Mixed Signal), Packaging & Testing related design issues, and SCL Foundry Process - Day 2 |
The Session will cover SCL Foundry Process Features and Capabilities |
SCL Team | 9-August-2024 | 181 |
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77 | Technical (Online) Session on Introduction to OpenPOWER by Dr. Hofstee (IBM) |
This Session will cover OpenPower ISA, including its origins in the first RISC architecture, the history of the different variants of the architecture, and its current state as an open architecture managed by the OpenPOWER project under the Linux foundation. The discussion will include how the POWER compliancy subsets allow license-free implementations from very small processors that can be used in microcontrollers to the versions of the architecture used in the largest SMP systems. |
IBM | 12-August-2024 | 122 |
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78 | Technical (Online) Session on OpenPower Microwatt microprocessor microarchitecture by Dr. Paul Mackerras (IBM) |
The Session will cover OpenPower Microwatt microprocessor microarchitecture. This talk provides a general overview of Microwatt and gives an introduction to the microarchitecture of the Microwatt processor, including variants that support the integer and floating-point subsets of the architecture. |
IBM | 13-August-2024 | 97 |
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79 | Technical Session on the registration process and MPW services offered by IMEC / EUROPRACTICE |
The session will cover registration process and MPW services offered by IMEC / EUROPRACTICE |
IMEC Team | 14-August-2024 | 81 |
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80 | Technical (Online) Session on Keysight ADS RF Microwave EDA Tool |
The Session will cover Power Amplifier Circuit Schematic design and simulation, Linear and Non-linear PA simulations, Impedance Matching tool, Smith Chart tool, Tuning and Optimization, Data Display, Parameter Sweeping, Design and Verification with Modulated Signals, Digital Pre-Distortion (DPD) Explorer etc. |
M/s. Keysight Technologies Pvt. Ltd | 16-August-2024 | 78 |
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81 | Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx - Day 1 |
The session will cover Zynq-7000 architecture and Pynq Z2, Overview of the Zynq UltraScale+ MPSoC architecture, Identifying the key elements of the application processing unit (APU) and real-time processing, unit (RPU),various power domains and their control structure, Introduction to the Quick Emulator (QEMU), which is the tool used to run software for a device etc. |
CoreEL Team | 19-August-2024 | 161 |
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82 | Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx - Day 2 |
Understanding how the PS and PL connect enables designers to create more efficient systems. Discussion on Peripherals on ZCU104 and Hands on Lab session etc. |
CoreEL Team | 20-August-2024 | 118 |
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83 | Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx - Day 3 |
Introduction and need for HLS, Using Vitis HLS, Basic design flow of Vitis HLS and review generated outputs, Improving Performance, Optimizing Performance through Pipelining, Data Types etc. |
CoreEL Team | 21-August-2024 | 117 |
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84 | Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx - Day 4 |
The session will cover Vitis Unified Software Platform Overview for Accelerator Development: Describes the elements of the development flow, such as software emulation, hardware emulation, and system run as well as debugging support for the host code and kernel code. Xilinx Runtime Library (XRT) Native APIs Describes the XRT native APIs used for opening a device, loading XCLBIN, creating buffers, executing a kernel, and controlling a graph etc. |
CoreEL Team | 22-August-2024 | 87 |
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85 | Technical (Online) Session on Formal Verification by Synopsys Team - Day 1 |
The session will cover design qualification with VC Spyglass Lint & with VC Spyglass CDC followed by demonstration. |
Synopsys Team | 26-August-2024 | 176 |
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86 | Technical (Online) Session on Formal Verification by Synopsys Team - Day 2 |
The session will cover dynamic HDL Simulations with VCS followed by demonstration. |
Synopsys Team | 27-August-2024 | 147 |
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87 | Technical (Online) Session on Formal Verification by Synopsys Team - Day 3 |
The session will cover simulation debug with Verdi automated debug system followed by the demonstration |
Synopsys Team | 28-August-2024 | 101 |
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88 | Online Interactive Session on Synopsys EDA Tools Installation by ChipIN Team |
The session would be covering issues related to installing the Synopsys EDA tools, accessing centrally hosted EDA licenses, setting up environment variables, support related, etc. |
Chpin Team | 29-August-2024 | 84 |
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89 | Technical (Online) Session on Introduction to Power Amplifier design |
The session will cover the Basics of Layout PA design in layout 3D view in layout & Introduction to RFPro, setting up EM simulation in RFPro, Advantages of RFPro over traditional emSetup, Generating test bench for EM circuit co-simulation etc. |
Keysight | 4-September-2024 | 88 |
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90 | Online Interactive Session on Implementing Unique Host-ID(s) for Effective EDA Tool Usage under C2S Programme |
The session would be covering the procedure for changing the hostname of the EDA linux server, host-ID format and FAQ's related to unique Host-ID(s) implementation etc. |
ChipIN Team | 6-September-2024 | 137 |
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91 | Technical (Online) Session on SCL's 180nm technology process (both 4-metal and 6-metal) by SCL Chandigarh |
The Session would cover the following topics:
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SCL Chandigarh | 10-September-2024 | 193 |
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92 | Technical (Online) Session on RTL to GDS Flow by using Cadence EDA Tool- Day 1 |
Introduction to IC Physical Design Flow, Cadence EDA tools for PD Flow, Functional Simulation using Incisive&Xcelium tool, Coverage analysis using IMC tool, RTL Synthesis using Genus Synthesis Solution, Synthesis Optimization for Power&Performance&Area, Logic Equivalence check using Conformal tool |
Entuple Team | 11-September-2024 | 341 |
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93 | Technical (Online) Session on RTL to GDS Flow by using Cadence EDA Tool- Day 2 |
Physical Implementation using Innovus that includes, Floor Planning, Power Planning, Placement, CTS, Routing, Timing Analysis using TEMPUS tool,Power Analysis VOLTUS tool, Parasitic Extraction,Generation of GDSII |
Entuple Team | 12-September-2024 | 149 |
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94 | Technical (Online) Session on Virtual SMART Lab |
The Session will cover SMARTLAB usage - VLSI & Embedded domain. |
NIELIT Calicut | 13-September-2024 | 48 |
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95 | Technical (Online) session Physical Design by ChipIN Team |
The session will cover the block level DRC, Dummy Fill, Chip level DRC, Antenna DRC and LVS etc. |
ChipIN Team | 17-September-2024 | 86 |
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96 | Technical (Online) session Physical Design by ChipIN Team |
The Session will cover Timing check with Tempus, using sdf generated from Innovus as well as from Virtuoso etc |
ChipIN Team | 20-September-2024 | 87 |
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97 | Technical (Online) session Physical Design by ChipIN Team |
The session will cover Pex extraction and Spice simulations using spectre&unisim and tapeout to SCL foundry |
ChipIN Team | 23-September-2024 | 97 |
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98 | Building 64-bit Microwatt OpenPOWER processor targeting Arty A7-100T FPGA Development Board |
During this presentation, a step-by-step walkthrough will be conducted to demonstrate how a full system can be built based on the open and free 64-bit OpenPOWER ISA "Microwatt" processor, targeting the Arty A7-100T FPGA development board. Although Microwatt can be used as a microcontroller due to its small size, it is powerful enough to run Linux.
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IBM | 24-September-2024 | 90 |
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99 | Technical (Online) Session on Introduction to Chiplet design using Keysight ADS Software |
Introduction to Chiplet |
Keysight Technology | 26-September-2024 | 67 |
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100 | Online Session on SCL 180nm Tapeout Process (November Shuttle) by SCL Chandigarh |
The Session willl discuss the process for filling out the "Silicon Number Generation Form" Understanding the all columns of the "Silicon Numbering Table" Completing all sections of "Process Information Sheet" for SCL 180nm, Detailed guidance on the tapeout submission form, including: General Guidelines for filling out the form, Layout Grid options, Instructions for "Process details" section, tapeout checklist, Reports to be included with design submissions tapeout and packaging guidelines |
SCL Chandigarh | 27-September-2024 | 126 |
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101 | MicroPython for Beginners |
Session Details [Click Here] |
NIELIT | 18-September-2024 |
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102 | RISC-V programming primer |
Will be announced |
NIELIT | - | ||
103 | Embedded for Beginners |
Session Details [Click Here] |
NIELIT | 10-October-2024 |
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104 | VLSI for Beginners |
Session Details [Click Here] |
NIELIT | 10-October-2024 |
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105 | Python for Beginners |
Session Details [Click Here] |
NIELIT | 10-October-2024 |
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106 | Introduction to MATLAB & Simulink |
Session Details [Click Here] |
NIELIT | 10-October-2024 |
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107 | Technical (Online) Session on ADS QuantumPro by Keysight |
The session will cover the Quantum Technology: An Overview, Quantum EDA at Keysight, Designing for Superconducting Qubits in ADS, QuantumPro, Designing for Basic Quantum Amplifiers |
M/s. Keysight Technologies Pvt. Ltd | 01-October-2024 | 31 |
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108 | Technical (Online) session on Ansys EDA Tool |
Introduction to the Power Analysis concepts, need of RTL power at early stage and inputs required for an RTL power analysis. It covers how PowerArtist Analyzes the RTL for average power, Introduction to PowerArtist GUI, interactive power debug feature using GUI. |
Ansys Team | 04-October-2024 | 64 |
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109 | Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool - Day 1 |
Installation of Xilinx EDA Tools, Overview of Xilinx FPGA architectures, FPGA and SoC boards, Vivado tool flow: Design entry, Simulation, Synthesis, Implementation and Programming, Introduction to IP Integrator and IP based Design etc. |
Xilinx/CoreEL | 07-October-2024 | 224 |
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110 | Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool - Day 2 |
Overview of Zynq-7000 and Zynq UltraScale+ MPSoC architectures, Vitis tool flow: Exporting hardware, platform and application project creation, Adding Peripherals and writing applications to access added peripherals, Working with DMA and Interrupts, Creating a Boot image etc. |
Xilinx/CoreEL | 08-October-2024 | 126 |
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111 | Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool - Day 3 |
Overview of Vitis HLS design flow, Basic design flow of Vitis HLS and review of generated outputs, Improving area and resource utilization, Creating a processor system using the IP created from HLS etc. |
Xilinx/CoreEL | 09-October-2024 | 102 |
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112 | Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool - Day 4 |
Introduction to Xilinx Platforms, Vitis for Acceleration Platforms and Vitis Design Analysis
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Xilinx/CoreEL | 10-October-2024 | 67 |
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113 | Technical (Online) Session on MPW Services and Other technical topics related to PDKs supported by M/s. IMEC |
MPW Services and Other technical topics related to PDKs supported by M/s. IMEC |
IMEC | 15-October-2024 | 117 |
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114 | Technical (Online) Session on SCL's 180nm foundry requirements with an example/sample design for the tapeout |
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SCL Chandigarh | 16-October-2024 | 113 |
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115 | Technnical (online) Session on System-level Simulation for RADAR/5G/Phased Array/SATCOM Applications |
System-level Simulation for RADAR/5G/Phased Array/SATCOM Applications |
Keysight | 17-October-2024 | 58 |
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116 | Technical (Online) Session on TCAD by Synopsys Team |
Day 1: Introduction to Technology Computer Aided Design (TCAD), Creating, Editing and Running Sentaurus Workbench projects, Visualizing TCAD simulation results using Sentaurus Visual etc. |
Synopsys Team | 21-October-2024 | 277 |
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117 | Technical (Online) Session on TCAD by Synopsys Team |
Day 2: Building a simple NMOS device from scratch in Sentaurus Process for device simulations, Overview of FinFET based CMOS inverter's process flow in Sentaurus Process Explorer, etc. |
Synopsys Team | 22-October-2024 | 206 |
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118 | Technical (Online) Session on TCAD by Synopsys Team |
Day 3: Simulating DC transfer and output characteristics of a MOSFET, Simulating AC characteristics of a MOSFET etc. |
Synopsys Team | 23-October-2024 | 145 |
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119 | Technical (Online) Session on Ansys Totem - Getting Started with Mixed-Signal (AMS) IP and SoC Power Integrity and Reliability Signoff |
The Session will cover electromigration Multiphysics sign-off solution for transistor-level and mixed-signal designs. |
Ansys Team | 28-October-2024 | 31 |
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120 | Technical (Online) session on Ansys EDA Tool |
The Session would cover the following topics:
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M/S Ansys | 07-November-2024 | 44 |
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121 | Technical (Online) Session on SCL's Chip-on-Board (CoB) packaging options offered for C2S participating institutions targeting SCL 180nm |
The session would cover the following CoB packaging details:
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SCL Chandigarh | 12-November-2024 | 80 |
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122 | Technical (Online) Session on SMART LAB by NIELIT Calicut |
The session aims to drive the advancement of VLSI and Embedded Systems design, fostering research and innovation in electronics development across the nation |
NIELIT Calicut | 14-November-2024 | 38 |
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