Technical session on SCL 180nm PDK

This technical session, will cover introduction to SCL PDK, Overview of Standard cells and IO cells from SCL used in Digital design., technical details and usage of Tech, LIB, and LEF files for standard and IO cells in the PDK within the digital design flow, technical details about map files, their usage, and importance, Physical verification (DRC, Antenna, LVS, PeX, etc.) with SCL PDK, Comprehensive overview of the Digital design flow with SCL PDK, Tapeout requirements for a Digital design with SCL PDK etc.

Technical Sessions by SCL on ASIC Design (Analog and Mixed Signal), Packaging & Testing related design issues, and SCL Foundry Process - Day 1

The Session will cover Analog and Mixed Signal ASIC Design Flow with SCL 180nm PDK and Packaging & Testing related design issues

Technical Sessions by SCL on ASIC Design (Analog and Mixed Signal), Packaging & Testing related design issues, and SCL Foundry Process - Day 2

The Session will cover SCL Foundry Process Features and Capabilities

Technical (Online) Session on SCL's 180nm technology process (both 4-metal and 6-metal) by SCL Chandigarh

The Session would cover the following topics:

• 1.8V, 3.3V, or 5V core CMOS
• 1.8V or 3.3V I/O library cells
• Single Poly and 4 to 6 metal layers
• High VT MOSFETs
• Deep N-well (isolated p-wells) for noise isolation
• Metal-Insulator-Metal (MIM) capacitors
• High-resistivity polysilicon resistors
• Selective cobalt salicidation
• Ti/TiN/AlCu/Ti/TiN metal interconnects
• 1.8V standard cells for logic design

Online Session on SCL 180nm Tapeout Process (November Shuttle) by SCL Chandigarh

The Session willl discuss the process for filling out the "Silicon Number Generation Form" Understanding the all columns of the "Silicon Numbering Table" Completing all sections of "Process Information Sheet" for SCL 180nm, Detailed guidance on the tapeout submission form, including: General Guidelines for filling out the form, Layout Grid options, Instructions for "Process details" section, tapeout checklist, Reports to be included with design submissions tapeout and packaging guidelines.

Technical (Online) Session on SCL's 180nm foundry requirements with an example/sample design for the tapeout

1. Grid size 0.005um settings
2. Powering the IC for IO and Core
3. Silicon Number with PCI insertion in the design
4. Layer revision block placement in the design
5. Seal-ring placement with GND connection
6. Dummy Fill with header
7. Pads connection till top metal (TOP_M)
8. Final Chip Origin placement at (0,0) after seal ring insertion
9. Making DRC clean
10. Making Antenna DRC clean
11. Generation of Devices type (or legal devices) used in layout report
12. Generation of List of all legal layers used before silicon number insertion in Excel Format (Layer Name + layer number + datatype)

• Architecture of Questa
• Design and Verification Language Support
• Understanding GUI Features
• Questa Modes
• Debugging with the Schematic Window
• Debugging with the Dataflow Window
• Waveform Comparison
• Code Coverage
• Demo on Questa Prime

• Questa Lint
• Questa AutoCheck

• Questa CoverCheck
• Questa CDC

• SupportNet Login Process
• Overview of the SupportNet web-portal
• Downloading Binaries - flow
• Overview of On-Demand Trainings (ODTs) on Siemens EDA Tools
• Registration Process for ODTs
• Accessing ODTs
• Service requests through SupportNet web-portal

• Schematic entry and Spectre Analysis
• Custom Layout Design, Verification and Post-Layout Analysis
• Virtuoso Initial Setup, Schematic Design, Pre-Layout Simulation Setup Using ADE Explorer and Assembler, Running Simulations, etc. (will be covered by Cadence Team)
• Dummy Transistors, Shielding, Latch-Up, Guard Ring, PCell Design for MOS & Passive Devices, Layout XL Overview, Post-Layout Simulation, etc. (will be covered by Cadence Team)

• ASIC flow overview, Significance of Synopsys tools in the entire flow, RTL design example - Synchronous and Asynchronous FIFO
• FIFO RTL coding, FIFO Functional verification using Verilog
• Lint and CDC, UPF implementation, Synthesis, Gate level simulation
• Introduction to HVL based TB, Develop SV and UVM TB for Asynchronous FIFO, Develop test cases
• Asynchronous FIFO, Develop test cases, Develop other TB components, Coverage analysis, Verdi tool debug

• Introduction to Big Data and SeaScape Platform, setting up RedHawk-SC and performing basic EM/IR Analysis and various methods for checking IR Power drops
• Hands-on lab session on RedHawk-SC

• FAQs about latest SCL PDK

• Introduction to DFT, Types of Test and fault models Basic Scan Test Scan Insertion Flow, ATPG Flow ATPG Demo, Introduction to Compression

• Installing the Keysight EDA tools, accessing centrally hosted EDA licenses, setting up environment variables, support related, etc.

• The Session will cover some of the sources of power- and energy-inefficiency in today's microprocessors. etc.

• RTL Coding guidelines
• Async. FIFO Design and Simulation using Xcellium Tool

• Linting Using Candence Jasper Gold

• Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) using Cadence Jasper Gold

• X - Propagation using Cadence Jasper Gold

Introduction to Calibre EDA Tool, DRC Setup and Rule Violations check etc.

Technical (Online) Session on Keysight Cliosoft Software (Design Data Management tool)

Importance of Design Data Management (DDM), Introduction to Cliosoft's revolutionary solutions, SOS's Simple Solutions to Big Problems, Data Security, Network Storage Optimization, Design and IP Reuse, Live Demo and Case Studies etc.

Technical (Online) session on SCL 180nm PDK and its integration into the design flow.

During this technical session, participants will have the opportunity to clarify their doubts and queries related to SCL PDK.

Technical (Online) Session on accessing and using Xilinx Alveo U 55C and VCK5000 Versal FPGA Boards.

Introduction to Xilinx Platforms, Intro to Vitis for Acceleration Platforms, Vitis Tool Flow, Vitis Design Analysis, Alveo U55C High Performance Compute Card, VCK5000 Versal Development Card etc.

Technical (Online) Session on Introduction to Keysight ADS and Schematic Software

Introductory session on Keysight ADS and Schematic EDA Software.

Technical (Online) Sessions on Synthesis and Post Synthesis Flow by ChipIN Team

Writing/Defining timing constraints for Async. FIFO Design, TCL scripting for Synthesis, and Genus Synthesis Tool Flow

Technical (Online) Sessions on Synthesis and Post Synthesis Flow by ChipIN Team

Logic Equivalence Check, post synthesis simulations, zero delay simulation, unit delay simulation and sdf simulations using Xcelium Tool

Technical Session on Questa simulator and Linting - Day 1

Questa Sim Introduction (Features and Flows), Questa Sim usage in GUI, Command line and in-built examples demo, Questa Sim Advanced features discussion, Advanced GUI -Coverage, Debug etc.

Technical Session Questa simulator and Linting - Day 2

Introduction to Questa Design solutions and Introduction to Linting, Questa Lint, Methodologies and goals, Advanced Features, Demo and Graphical user interface, Queries etc.

Ansys Technical Session on Totem EDA Tool

The session will cover Totem Platform Overview, Totem Static Analysis, Totem Dynamic Analysis, Analysis, IP Model Creation, GUI Wizard etc.

Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 1

The Session Covers the Start of Physical Design: Import, Floorplan, IO fillers, and Power plan, creation of IO assignment file, MMMC file (GUI + Script) using Innovus Tool

Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 2

The session covers the Placement, Clock Tree Synthesis and STA: Placement, Creation of Clock tree spec file, CTS (Cluster, trial and full mode) and ECO to fix STA if any

Online Session on Installing the Latest Shared SCL PDK by ChipIN Team

During this technical session, participants will have the opportunity to clarify their doubts and queries related to SCL PDK installation.

Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 3

The session will cover the Routing, std. cell fillers and Sign-off, ECO post route and sign-off, Post Route netlist simulations, zero delay simulation, unit delay simulation, back annotation with sdf

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 1

The session will cover Custom Compiler Overview, Library Manager, Schematic Editor, Symbol Creation etc.

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 2

The session will cover PrimeWave Design Environment and Simulation etc.

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 3

The session will cover PrimeSim Continuum

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 4

The session will cover Layout Editor, SDL.

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 5

The session will cover Physical Verification and Parasitic Extraction

Technical (Online) session on SCL 180nm PDK

This technical session, will cover introduction to SCL PDK, Overview of Standard cells and IO cells from SCL used in Digital design., technical details and usage of Tech, LIB, and LEF files for standard and IO cells in the PDK within the digital design flow, technical details about map files, their usage, and importance, Physical verification (DRC, Antenna, LVS, PeX, etc.) with SCL PDK, Comprehensive overview of the Digital design flow with SCL PDK, Tapeout requirements for a Digital design with SCL PDK etc.

Technical (Online) Session on Keysight ADS HDS Software

Technical session on Keysight ADS HSD-High Speed Simulation: Signal Integrity, Power Integrity, Memory Design

Technical (Online) Session on Ansys PowerArtist EDA Tool

Introduction to PowerArtist, Steps to Power-Efficient RTL Design, Power Computation Fundamentals; PowerArtist Setup and Flow, RTL Import - "Elaborate", Perform Architectural Trade-Offs (Explore Power of Micro-Architectures); Static Power Efficiency Audit - "AnalyzeStaticEfficiency", Profile Real Application Scenarios (Vector Analysis and Power Profiling), Check Power versus Budget Early (Average and Time-Based Power Analysis), Visually Debug Power for Anomalies, Reduce Power using RTL Techniques etc.

Embedded for Beginners

Session Details [Click Here]

VLSI for Beginners

Session Details [Click Here]

Python for Beginners

Session Details [Click Here]

Introduction to MATLAB & Simulink

Session Details [Click Here]

Machine Learning using Python

Session Details [Click Here]

Online interactive session on EDA Tools installation

The session would be covering issues related to installing the Synopsys EDA tools, accessing centrally hosted EDA licenses, setting up environment variables, support related, etc.

MicroPython for Beginners

Session Details [Click Here]

Technical (Online) Session on Cadence Innovus EDA Tool

Introduction to Semi-Custom IC Design Flow (RTL-GDSII), Physical Design process and tool flow, Data interpretation for Physical Design, Physical design flow for Block and Chip level etc. Physical Implementation using Innovus that includes, Floor Planning, Power Planning, Placement, CTS, Routing, Timing and Power Analysis, Physical Verification etc.

Technical (Online) Session on Physical Design Tool flow - Day 1

The session will cover LEC check for synthesis netlist with post route netlist, Post Route netlist simulations, zero delay simulation, unit delay simulation, back annotation with sdf

Technical (Online) Session on Physical Design Tool flow - Day 2

The session will cover std. cells, io cells, fifo GDS-II stream in Virtuoso, silicon number insertion and seal-ring placement etc.

Online interactive session on Xilinx EDA Tools installation by CoreEL Team

The session would be covering overview of EDA Tools from AMD-Xilinx, Tool installation procedure, License acquisition procedure, frequently encountered issues, and solutions etc.

Technical (Online) Session on RTL to GDS Flow - Day 1

RTL to GDS Flow

Technical (Online) Session on RTL to GDS Flow - Day 2

RTL to GDS Flow

Technical (Online) Session on RTL to GDS Flow - Day 3

RTL to GDS Flow

Technical (Online) Session on RTL to GDS Flow - Day 4

RTL to GDS Flow

Technical (Online) Session on RTL to GDS Flow - Day 5

RTL to GDS Flow

Embedded for Beginners

Session Details [Click Here]

VLSI for Beginners

Session Details [Click Here]

Python for Beginners

Session Details [Click Here]

Introduction to MATLAB & Simulink

Session Details [Click Here]

MicroPython for Beginners

Session Details [Click Here]

RISC-V programming primer

-

Machine Learning using Python

Session Details [Click Here]

Data Analysis Using Python

Session Details [Click Here]

Technical Sessions by SCL on ASIC Design (Analog and Mixed Signal), Packaging & Testing related design issues, and SCL Foundry Process - Day 1

The Session will cover Analog and Mixed Signal ASIC Design Flow with SCL 180nm PDK and Packaging & Testing related design issues

Technical Sessions by SCL on ASIC Design (Analog and Mixed Signal), Packaging & Testing related design issues, and SCL Foundry Process - Day 2

The Session will cover SCL Foundry Process Features and Capabilities

Technical (Online) Session on Introduction to OpenPOWER by Dr. Hofstee (IBM)

This Session will cover OpenPower ISA, including its origins in the first RISC architecture, the history of the different variants of the architecture, and its current state as an open architecture managed by the OpenPOWER project under the Linux foundation. The discussion will include how the POWER compliancy subsets allow license-free implementations from very small processors that can be used in microcontrollers to the versions of the architecture used in the largest SMP systems.

Technical (Online) Session on OpenPower Microwatt microprocessor microarchitecture by Dr. Paul Mackerras (IBM)

The Session will cover OpenPower Microwatt microprocessor microarchitecture. This talk provides a general overview of Microwatt and gives an introduction to the microarchitecture of the Microwatt processor, including variants that support the integer and floating-point subsets of the architecture.

Technical Session on the registration process and MPW services offered by IMEC / EUROPRACTICE

The session will cover registration process and MPW services offered by IMEC / EUROPRACTICE

Technical (Online) Session on Keysight ADS RF Microwave EDA Tool

The Session will cover Power Amplifier Circuit Schematic design and simulation, Linear and Non-linear PA simulations, Impedance Matching tool, Smith Chart tool, Tuning and Optimization, Data Display, Parameter Sweeping, Design and Verification with Modulated Signals, Digital Pre-Distortion (DPD) Explorer etc.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx - Day 1

The session will cover Zynq-7000 architecture and Pynq Z2, Overview of the Zynq UltraScale+ MPSoC architecture, Identifying the key elements of the application processing unit (APU) and real-time processing, unit (RPU),various power domains and their control structure, Introduction to the Quick Emulator (QEMU), which is the tool used to run software for a device etc.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx - Day 2

Understanding how the PS and PL connect enables designers to create more efficient systems. Discussion on Peripherals on ZCU104 and Hands on Lab session etc.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx - Day 3

Introduction and need for HLS, Using Vitis HLS, Basic design flow of Vitis HLS and review generated outputs, Improving Performance, Optimizing Performance through Pipelining, Data Types etc.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx - Day 4

The session will cover Vitis Unified Software Platform Overview for Accelerator Development: Describes the elements of the development flow, such as software emulation, hardware emulation, and system run as well as debugging support for the host code and kernel code. Xilinx Runtime Library (XRT) Native APIs Describes the XRT native APIs used for opening a device, loading XCLBIN, creating buffers, executing a kernel, and controlling a graph etc.

Technical (Online) Session on Formal Verification by Synopsys Team - Day 1

The session will cover design qualification with VC Spyglass Lint & with VC Spyglass CDC followed by demonstration.

Technical (Online) Session on Formal Verification by Synopsys Team - Day 2

The session will cover dynamic HDL Simulations with VCS followed by demonstration.

Technical (Online) Session on Formal Verification by Synopsys Team - Day 3

The session will cover simulation debug with Verdi automated debug system followed by the demonstration

Online Interactive Session on Synopsys EDA Tools Installation by ChipIN Team

The session would be covering issues related to installing the Synopsys EDA tools, accessing centrally hosted EDA licenses, setting up environment variables, support related, etc.

Technical (Online) Session on Introduction to Power Amplifier design

The session will cover the Basics of Layout PA design in layout 3D view in layout & Introduction to RFPro, setting up EM simulation in RFPro, Advantages of RFPro over traditional emSetup, Generating test bench for EM circuit co-simulation etc.

Online Interactive Session on Implementing Unique Host-ID(s) for Effective EDA Tool Usage under C2S Programme

The session would be covering the procedure for changing the hostname of the EDA linux server, host-ID format and FAQ's related to unique Host-ID(s) implementation etc.

Technical (Online) Session on SCL's 180nm technology process (both 4-metal and 6-metal) by SCL Chandigarh

The Session would cover the following topics:

• 1.8V, 3.3V, or 5V core CMOS
• 1.8V or 3.3V I/O library cells
• Single Poly and 4 to 6 metal layers
• High VT MOSFETs
• Deep N-well (isolated p-wells) for noise isolation
• Metal-Insulator-Metal (MIM) capacitors
• High-resistivity polysilicon resistors
• Selective cobalt salicidation
• Ti/TiN/AlCu/Ti/TiN metal interconnects
• 1.8V standard cells for logic design

Technical (Online) Session on RTL to GDS Flow by using Cadence EDA Tool- Day 1

Introduction to IC Physical Design Flow, Cadence EDA tools for PD Flow, Functional Simulation using Incisive&Xcelium tool, Coverage analysis using IMC tool, RTL Synthesis using Genus Synthesis Solution, Synthesis Optimization for Power&Performance&Area, Logic Equivalence check using Conformal tool

Technical (Online) Session on RTL to GDS Flow by using Cadence EDA Tool- Day 2

Physical Implementation using Innovus that includes, Floor Planning, Power Planning, Placement, CTS, Routing, Timing Analysis using TEMPUS tool,Power Analysis VOLTUS tool, Parasitic Extraction,Generation of GDSII

Technical (Online) Session on Virtual SMART Lab

The Session will cover SMARTLAB usage - VLSI & Embedded domain.

Technical (Online) session Physical Design by ChipIN Team

The session will cover the block level DRC, Dummy Fill, Chip level DRC, Antenna DRC and LVS etc.

Technical (Online) session Physical Design by ChipIN Team

The Session will cover Timing check with Tempus, using sdf generated from Innovus as well as from Virtuoso etc

Technical (Online) session Physical Design by ChipIN Team

The session will cover Pex extraction and Spice simulations using spectre&unisim and tapeout to SCL foundry

Building 64-bit Microwatt OpenPOWER processor targeting Arty A7-100T FPGA Development Board

During this presentation, a step-by-step walkthrough will be conducted to demonstrate how a full system can be built based on the open and free 64-bit OpenPOWER ISA "Microwatt" processor, targeting the Arty A7-100T FPGA development board. Although Microwatt can be used as a microcontroller due to its small size, it is powerful enough to run Linux.

For this walkthrough, compute infrastructure at C-DAC will be leveraged to create the FPGA configuration bitfile. However, a full set of instructions will also be provided to perform the build, starting from a basic installation of Ubuntu 22.04.4.

The PowerPC architecture and the microarchitecture of the Microwatt processor were covered in previous sessions and will be briefly summarized. Additional background on the SoC architecture and the various tools used to build the Microwatt-based system will also be provided during the walkthrough.

Technical (Online) Session on Introduction to Chiplet design using Keysight ADS Software

Introduction to Chiplet
Benefits of Chiplet
Analyze Signal Integrity for Chiplet using UCIe standards
Use ADS and perform Die2Die simulation as per UCIe standards
Pre and Post layout Chiplet simulation in ADS

Online Session on SCL 180nm Tapeout Process (November Shuttle) by SCL Chandigarh

The Session willl discuss the process for filling out the "Silicon Number Generation Form" Understanding the all columns of the "Silicon Numbering Table" Completing all sections of "Process Information Sheet" for SCL 180nm, Detailed guidance on the tapeout submission form, including: General Guidelines for filling out the form, Layout Grid options, Instructions for "Process details" section, tapeout checklist, Reports to be included with design submissions tapeout and packaging guidelines

MicroPython for Beginners

Session Details [Click Here]

RISC-V programming primer

Will be announced

Embedded for Beginners

Session Details [Click Here]

VLSI for Beginners

Session Details [Click Here]

Python for Beginners

Session Details [Click Here]

Introduction to MATLAB & Simulink

Session Details [Click Here]

Technical (Online) Session on ADS QuantumPro by Keysight

The session will cover the Quantum Technology: An Overview, Quantum EDA at Keysight, Designing for Superconducting Qubits in ADS, QuantumPro, Designing for Basic Quantum Amplifiers

Technical (Online) session on Ansys EDA Tool

Introduction to the Power Analysis concepts, need of RTL power at early stage and inputs required for an RTL power analysis. It covers how PowerArtist Analyzes the RTL for average power, Introduction to PowerArtist GUI, interactive power debug feature using GUI.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool - Day 1

Installation of Xilinx EDA Tools, Overview of Xilinx FPGA architectures, FPGA and SoC boards, Vivado tool flow: Design entry, Simulation, Synthesis, Implementation and Programming, Introduction to IP Integrator and IP based Design etc.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool - Day 2

Overview of Zynq-7000 and Zynq UltraScale+ MPSoC architectures, Vitis tool flow: Exporting hardware, platform and application project creation, Adding Peripherals and writing applications to access added peripherals, Working with DMA and Interrupts, Creating a Boot image etc.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool - Day 3

Overview of Vitis HLS design flow, Basic design flow of Vitis HLS and review of generated outputs, Improving area and resource utilization, Creating a processor system using the IP created from HLS etc.

Four-day Online Technical Training Sessions on FPGA Boards and Xilinx EDA Tool - Day 4

Introduction to Xilinx Platforms, Vitis for Acceleration Platforms and Vitis Design Analysis

• Vitis Unified Software Platform Overview for Accelerator Development
• Xilinx Alveo U55C and VCK5000 Versal FPGA Boards
• Creating Vitis Project on both AI Engines and the Adaptable Engine using Vector Add

Technical (Online) Session on MPW Services and Other technical topics related to PDKs supported by M/s. IMEC

MPW Services and Other technical topics related to PDKs supported by M/s. IMEC

Technical (Online) Session on SCL's 180nm foundry requirements with an example/sample design for the tapeout

1. Grid size 0.005um settings
2. Powering the IC for IO and Core
3. Silicon Number with PCI insertion in the design
4. Layer revision block placement in the design
5. Seal-ring placement with GND connection
6. Dummy Fill with header
7. Pads connection till top metal (TOP_M)
8. Final Chip Origin placement at (0,0) after seal ring insertion
9. Making DRC clean
10. Making Antenna DRC clean
11. Generation of Devices type (or legal devices) used in layout report
12. Generation of List of all legal layers used before silicon number insertion in Excel Format (Layer Name + layer number + datatype)

Technnical (online) Session on System-level Simulation for RADAR/5G/Phased Array/SATCOM Applications

System-level Simulation for RADAR/5G/Phased Array/SATCOM Applications

Technical (Online) Session on TCAD by Synopsys Team

Day 1: Introduction to Technology Computer Aided Design (TCAD), Creating, Editing and Running Sentaurus Workbench projects, Visualizing TCAD simulation results using Sentaurus Visual etc.

Technical (Online) Session on TCAD by Synopsys Team

Day 2: Building a simple NMOS device from scratch in Sentaurus Process for device simulations, Overview of FinFET based CMOS inverter's process flow in Sentaurus Process Explorer, etc.

Technical (Online) Session on TCAD by Synopsys Team

Day 3: Simulating DC transfer and output characteristics of a MOSFET, Simulating AC characteristics of a MOSFET etc.

Technical (Online) Session on Ansys Totem - Getting Started with Mixed-Signal (AMS) IP and SoC Power Integrity and Reliability Signoff

The Session will cover electromigration Multiphysics sign-off solution for transistor-level and mixed-signal designs.