• Architecture of Questa
• Design and Verification Language Support
• Understanding GUI Features
• Questa Modes
• Debugging with the Schematic Window
• Debugging with the Dataflow Window
• Waveform Comparison
• Code Coverage
• Demo on Questa Prime

• Questa Lint
• Questa AutoCheck

• Questa CoverCheck
• Questa CDC

• SupportNet Login Process
• Overview of the SupportNet web-portal
• Downloading Binaries - flow
• Overview of On-Demand Trainings (ODTs) on Siemens EDA Tools
• Registration Process for ODTs
• Accessing ODTs
• Service requests through SupportNet web-portal

• Schematic entry and Spectre Analysis
• Custom Layout Design, Verification and Post-Layout Analysis
• Virtuoso Initial Setup, Schematic Design, Pre-Layout Simulation Setup Using ADE Explorer and Assembler, Running Simulations, etc. (will be covered by Cadence Team)
• Dummy Transistors, Shielding, Latch-Up, Guard Ring, PCell Design for MOS & Passive Devices, Layout XL Overview, Post-Layout Simulation, etc. (will be covered by Cadence Team)

• ASIC flow overview, Significance of Synopsys tools in the entire flow, RTL design example - Synchronous and Asynchronous FIFO
• FIFO RTL coding, FIFO Functional verification using Verilog
• Lint and CDC, UPF implementation, Synthesis, Gate level simulation
• Introduction to HVL based TB, Develop SV and UVM TB for Asynchronous FIFO, Develop test cases
• Asynchronous FIFO, Develop test cases, Develop other TB components, Coverage analysis, Verdi tool debug

• Introduction to Big Data and SeaScape Platform, setting up RedHawk-SC and performing basic EM/IR Analysis and various methods for checking IR Power drops
• Hands-on lab session on RedHawk-SC

• FAQs about latest SCL PDK

• Introduction to DFT, Types of Test and fault models Basic Scan Test Scan Insertion Flow, ATPG Flow ATPG Demo, Introduction to Compression

• Installing the Keysight EDA tools, accessing centrally hosted EDA licenses, setting up environment variables, support related, etc.

• The Session will cover some of the sources of power- and energy-inefficiency in today's microprocessors. etc.

• RTL Coding guidelines
• Async. FIFO Design and Simulation using Xcellium Tool

• Linting Using Candence Jasper Gold

• Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) using Cadence Jasper Gold

• X - Propagation using Cadence Jasper Gold

Introduction to Calibre EDA Tool, DRC Setup and Rule Violations check etc.

Technical (Online) Session on Keysight Cliosoft Software (Design Data Management tool)

Importance of Design Data Management (DDM), Introduction to Cliosoft's revolutionary solutions, SOS's Simple Solutions to Big Problems, Data Security, Network Storage Optimization, Design and IP Reuse, Live Demo and Case Studies etc.

Technical (Online) session on SCL 180nm PDK and its integration into the design flow.

During this technical session, participants will have the opportunity to clarify their doubts and queries related to SCL PDK.

Technical (Online) Session on accessing and using Xilinx Alveo U 55C and VCK5000 Versal FPGA Boards.

Introduction to Xilinx Platforms, Intro to Vitis for Acceleration Platforms, Vitis Tool Flow, Vitis Design Analysis, Alveo U55C High Performance Compute Card, VCK5000 Versal Development Card etc.

Technical (Online) Session on Introduction to Keysight ADS and Schematic Software

Introductory session on Keysight ADS and Schematic EDA Software.

Technical (Online) Sessions on Synthesis and Post Synthesis Flow by ChipIN Team

Writing/Defining timing constraints for Async. FIFO Design, TCL scripting for Synthesis, and Genus Synthesis Tool Flow

Technical (Online) Sessions on Synthesis and Post Synthesis Flow by ChipIN Team

Logic Equivalence Check, post synthesis simulations, zero delay simulation, unit delay simulation and sdf simulations using Xcelium Tool

Technical Session on Questa simulator and Linting - Day 1

Questa Sim Introduction (Features and Flows), Questa Sim usage in GUI, Command line and in-built examples demo, Questa Sim Advanced features discussion, Advanced GUI -Coverage, Debug etc.

Technical Session Questa simulator and Linting - Day 2

Introduction to Questa Design solutions and Introduction to Linting, Questa Lint, Methodologies and goals, Advanced Features, Demo and Graphical user interface, Queries etc.

Ansys Technical Session on Totem EDA Tool

The session will cover Totem Platform Overview, Totem Static Analysis, Totem Dynamic Analysis, Analysis, IP Model Creation, GUI Wizard etc.