Awareness Session on Intellectual Property Rights (IPR) for C2S Participating Institutes

Technical (Online) Awareness Session on Intellectual Property Rights (IPR) for C2S Participating Institutions

Technical (Online) Session on Device Modelling Solution by Keysight

This session will provide a general overview of Keysight Device Modeling tools for semiconductor devices: The Integrated Circuit Characterization and Analysis Program (IC-CAP).

Device Modeling IC-CAP software is the industry standard for semiconductor device modeling and characterization. It extracts accurate compact models for high speed/digital, analog, power electronics, and power RF applications. It enables foundries and integrated device manufacturers (IDMs) to streamline semiconductor device modeling workflows for silicon CMOS, Bipolar, compound gallium arsenide (GaAs), gallium nitride (GaN) and many other IC devices of the following key features:

Open device modeling software architecture enhances accuracy and flexibility to create and automate measurement, extraction and verification procedures. Turnkey extraction solutions for industry standard CMOS models, such as BSIM3/BSIM4, PSP and HiSIM,. minimize the learning curve and maximize model accuracy. Direct links to major commercial simulators ensure consistency between extracted models and the simulators used by circuit designers.

Technical Session on Getting Started with Ansys Totem EDA Tool

Introduction to Totem AMS platform Static Power Integrity EMIR Analysis Environment variables to setup and run Totem Totem GUI Totem Text Reports Totem Results Overview and Debug Introduction to Dynamic EMIR Analysis

Technical (Online) Session on SCL 180nm 4-metal and 6-metal processes by SCL Chandigarh

The session covers the following topics:

• Capabilities of SCLs 4-metal process
• Capabilities of SCLs 6-metal process
• Guidelines for selecting between the 4-metal and 6-metal processes based on design complexity and application
• Challenges associated with the 6-metal fabrication process

Technical (Online) Session on UTMOST4, Gateway, SmartSpice & Expert EDA Tool by M/s Silvaco

The session covers the following topics:

• UTMOST4
• Gateway and SmartSpeice
• Expert

Four-day Online Technical Training Session on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx

Day 1 :

• Vitis Tool Flow: Introduction to the Vitis Unified Software Platform: Explains how software/hardware engineers and application developers can benefit from the Vitis unified software environment and OpenCL framework
• Vitis Unified Software Platform Overview for Accelerator Development: Describes the elements of the development flow, such as software emulation, hardware emulation, and system run as well as debugging support for the host code and kernel code

Four-day Online Technical Training Session on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx

Day 2 :

• Introduction to Hardware Acceleration: Outlines the fundamental aspects of FPGAs, SoCs, and ACAPs that are required to guide the Vitis tool to the best computational architecture for any algorithm
• Vitis Execution Model and XRT: Describes the XRT and the OpenCL APIs used for setting up the platform, executing the target device, and post-processing
• Xilinx Runtime Library (XRT) Native APIs: Describes the XRT native APIs used for opening a device, loading XCLBIN, creating buffers, executing a kernel, and controlling a graph

Four-day Online Technical Training Session on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx

Day 3 :

• Design Analysis: Profiling: Describes the different reports generated by the tool and how to view the reports that help to optimize data transfer and kernel optimization using the Vitis analyzer tool
• Debugging: Explains the support for debugging host code and kernel code as well as tips to debug the system
• Kernel Development: Introduction to C/C++ based Kernels, Describes the trade-offs between C/C++, OpenCL, and RTL applications and the benefits of C-based kernels

Four-day Online Technical Training Session on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx

Day 4 :

• Kernel Development: Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators: Describes how the Vitis unified software development provides RTL kernel developers with a framework to integrate their hardware functions into an application running on a host PC connected to an FPGA via a PCIe® interface
• Optimizing the Performance of the Design: Illustrates various optimization techniques, such as optimizing the host code and data transfer between kernels and global memory, to improve kernel performance