Four-day Online Technical Training Session on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx

Day 1 :

• Vitis Tool Flow: Introduction to the Vitis Unified Software Platform: Explains how software/hardware engineers and application developers can benefit from the Vitis unified software environment and OpenCL framework
• Vitis Unified Software Platform Overview for Accelerator Development: Describes the elements of the development flow, such as software emulation, hardware emulation, and system run as well as debugging support for the host code and kernel code

Four-day Online Technical Training Session on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx

Day 2 :

• Introduction to Hardware Acceleration: Outlines the fundamental aspects of FPGAs, SoCs, and ACAPs that are required to guide the Vitis tool to the best computational architecture for any algorithm
• Vitis Execution Model and XRT: Describes the XRT and the OpenCL APIs used for setting up the platform, executing the target device, and post-processing
• Xilinx Runtime Library (XRT) Native APIs: Describes the XRT native APIs used for opening a device, loading XCLBIN, creating buffers, executing a kernel, and controlling a graph

Four-day Online Technical Training Session on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx

Day 3 :

• Design Analysis: Profiling: Describes the different reports generated by the tool and how to view the reports that help to optimize data transfer and kernel optimization using the Vitis analyzer tool
• Debugging: Explains the support for debugging host code and kernel code as well as tips to debug the system
• Kernel Development: Introduction to C/C++ based Kernels, Describes the trade-offs between C/C++, OpenCL, and RTL applications and the benefits of C-based kernels

Four-day Online Technical Training Session on FPGA Boards and Xilinx EDA Tool by CoreEL/Xilinx

Day 4 :

• Kernel Development: Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators: Describes how the Vitis unified software development provides RTL kernel developers with a framework to integrate their hardware functions into an application running on a host PC connected to an FPGA via a PCIe® interface
• Optimizing the Performance of the Design: Illustrates various optimization techniques, such as optimizing the host code and data transfer between kernels and global memory, to improve kernel performance