Technical (Online) session on SCL 180nm PDK and its integration into the design flow.

During this technical session, participants will have the opportunity to clarify their doubts and queries related to SCL PDK.

Technical (Online) Session on accessing and using Xilinx Alveo U 55C and VCK5000 Versal FPGA Boards.

Introduction to Xilinx Platforms, Intro to Vitis for Acceleration Platforms, Vitis Tool Flow, Vitis Design Analysis, Alveo U55C High Performance Compute Card, VCK5000 Versal Development Card etc.

Technical (Online) Session on Introduction to Keysight ADS and Schematic Software

Introductory session on Keysight ADS and Schematic EDA Software.

Technical (Online) Sessions on Synthesis and Post Synthesis Flow by ChipIN Team

Writing/Defining timing constraints for Async. FIFO Design, TCL scripting for Synthesis, and Genus Synthesis Tool Flow

Technical (Online) Sessions on Synthesis and Post Synthesis Flow by ChipIN Team

Logic Equivalence Check, post synthesis simulations, zero delay simulation, unit delay simulation and sdf simulations using Xcelium Tool

Technical Session on Questa simulator and Linting - Day 1

Questa Sim Introduction (Features & Flows), Questa Sim usage in GUI, Command line & in-built examples demo, Questa Sim Advanced features discussion, Advanced GUI -Coverage, Debug etc.

Technical Session Questa simulator and Linting - Day 2

Introduction to Questa Design solutions and Introduction to Linting, Questa Lint, Methodologies and goals, Advanced Features, Demo and Graphical user interface, Queries etc.

Ansys Technical Session on Totem EDA Tool

The session will cover Totem Platform Overview, Totem Static Analysis, Totem Dynamic Analysis, Analysis, IP Model Creation, GUI Wizard etc.

Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 1

The Session Covers the Start of Physical Design: Import, Floorplan, IO fillers, and Power plan, creation of IO assignment file, MMMC file (GUI + Script) using Innovus Tool

Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 2

The session covers the Placement, Clock Tree Synthesis and STA: Placement, Creation of Clock tree spec file, CTS (Cluster, trial and full mode) and ECO to fix STA if any

Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 3

The session will cover the Routing, std. cell fillers and Sign-off, ECO post route and sign-off, Post Route netlist simulations, zero delay simulation, unit delay simulation, back annotation with sdf

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 1

The session will cover Custom Compiler Overview, Library Manager, Schematic Editor, Symbol Creation etc.

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 2

The session will cover PrimeWave Design Environment and Simulation etc.

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 3

The session will cover PrimeSim Continuum

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 4

The session will cover Layout Editor, SDL.

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 5

The session will cover Physical Verification and Parasitic Extraction