Technical (Online) Session on Getting Started with Renesas QuickConnect Studio

This session teaches students and educators how to set up QuickConnect Studio and educators to request for QuickConnect Kits for hands-on, project-based learning in embedded systems. Learn how to:

• Create a QuickConnect account and access the platform
• Guide educators to request for QuickConnect kits using form
• Navigate the QuickConnect Studio's interface and workflows

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Technical (Online) Session on "VEGA Processors: India's Indigenous RISC-V Based Computing Revolution"

This session will introduce the core principles of the RISC-V Instruction Set Architecture (ISA) and explore the different processor variants within the RISC-V ecosystem. It will also discuss the range of peripheral IPs commonly integrated into SoC designs. Participants will gain an understanding of the architecture and integration approach of VEGA-based SoCs, as well as the design and verification processes adopted for these systems. The session will further highlight the validation strategies and methodologies employed to ensure dependable and high-quality SoC development.

Two-Days Technical (Online) Session on TCL Script: Automation for Cadence's Xcelium Tool by Entuple Team - Day 1

Session-1: Introduction & Overview

• Introduction to the Xcelium Tcl console and interactive modes
• Tcl syntax essentials for simulation control
• Navigating design hierarchy and querying objects
• Tool demo: Use Tcl commands to explore design data

Session-2: Automation Simulation setup and Demo

• Environment and path configuration
• Automating simulation run, compile, and elaboration steps
• Handling files and variables for testbench setup

Two-Days Technical (Online) Session on TCL Script: Automation for Cadence's Xcelium Tool by Entuple Team - Day 2

Session-3: Debugging and Analysis

• Driver tracing and breakpoint control via Tcl
• Glitch debug and waveform inspection commands
• Handling simulation hangs or infinite loops
• Tool Demo: Use Tcl to trace signal drivers and debug a simulation

Session-4: Scripting and Tool Demo

• Save and restart simulation sessions using Tcl procedures
• Deposit and force command applications
• Scripting repetitive debug tasks and report generation
• Tool demo: Create a Tcl macro to capture checkpoints, and auto-generate debug reports

Technical (Online) Workshop on Altium- Mastering the Fundamentals

This hands-on workshop covers the complete PCB design process using Altium Designer and Altium 365, from schematic creation to manufacturing files and cloud collaboration.

• Quick revision of PCB fundamentals and Altium overview
• Creating a schematic, placing components, and running ERC
• Translating schematic to PCB and understanding layer stack-up
• Component placement, routing, and performing DRC
• Generating and verifying Gerber files
• Exploring Altium 365 for project sharing and collaboration

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Technical Online Session High-Gain Telescopic OpAmp Circuit Design Post-Layout Simulations, IO Pad-Ring & Seal-Ring Integration with Core by ChipIN Team

The Session will cover the following topics:

• Hands-on Lab session on post-layout simulations to validate performance.
• Designing pad-ring, seal-ring, dummy fill and related blocks etc.

Technical Online Session on Full-Chip Simulation & Physical Verification Using Cadence Virtuoso & Siemens Calibre Tools by ChipIN Team

The Session will cover the following topics:

• The session will cover core + IO simulations of High-Gain Telescopic OpAmp Circuit Design.
• Final full-chip verification.