Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 1

The Session Covers the Start of Physical Design: Import, Floorplan, IO fillers, and Power plan, creation of IO assignment file, MMMC file (GUI + Script) using Innovus Tool

Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 2

The session covers the Placement, Clock Tree Synthesis and STA: Placement, Creation of Clock tree spec file, CTS (Cluster, trial and full mode) and ECO to fix STA if any

Online Session on Installing the Latest Shared SCL PDK by ChipIN Team

During this technical session, participants will have the opportunity to clarify their doubts and queries related to SCL PDK installation.

Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 3

The session will cover the Routing, std. cell fillers and Sign-off, ECO post route and sign-off, Post Route netlist simulations, zero delay simulation, unit delay simulation, back annotation with sdf

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 1

The session will cover Custom Compiler Overview, Library Manager, Schematic Editor, Symbol Creation etc.

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 2

The session will cover PrimeWave Design Environment and Simulation etc.

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 3

The session will cover PrimeSim Continuum

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 4

The session will cover Layout Editor, SDL.

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 5

The session will cover Physical Verification and Parasitic Extraction