C2S
Home Upcoming Sessions-2025

Upcoming Training Sessions organized by ChipIN Centre for Participating Institutions under C2S Programme

Archive
# TOPIC SESSION DETAILS PRESENTER DATE NO. OF ATTENDEES FEEDBACK
1

Two-Days Technical (Online) Session on "Pads professional and Analysis" by CoreEL Team - Day 1

The session will covers the following topics :

  • Library Management & Schematic Design Training
    • Creating and accessing a new library
    • Understanding library flow
    • Navigating the GUI
    • Creating schematic symbols, padstacks, and footprints
    • Building parts
    • Library services
    • Part Quest
    • Group discussion / Q&A
  • Designer -Schematic Creation
    • Project creation, Library mapping, Display and backup settings
    • Component placement strategies, Net connections, Creating groups or clusters
    • Forward annotation to PCB layout
    • Constraint management, BOM (Bill of Materials) creation
    • Q&A
CoreEL Team 12-Jan-2026
2

Two-Days Technical (Online) Session on "Pads professional and Analysis" by CoreEL Team - Day 2

The Session will covers the following topics :

  • PADS Professional PCB Layout Training
    • Defining board outlines, Component placement strategies
    • Display control settings, Manual routing and semi-auto routing
    • Constraint Manager & Editor, Editor controls
    • Design rule checks (DRC) and verification
    • Manufacturing output generation (Gerber, ODB++ etc.)
    • Group discussion / Q&A
  • Analysis Training
    • Power Integrity analysis: DC drop Analysis, Thermal Analysis, AC analysis (PDN)
    • Signal integrity analysis : Interactive simulation, General batch wizard, Termination optimization, DDRx analysis, SerDes batch analysis, S-parameter extraction etc.
CoreEL Team 13-Jan-2026
3

Technical (Online) Session on "From Transistors to VIP: The Verification Journey in Chip Design" by Cadence Team

The session covers the following topics :

  • From Transistors to Chips
  • Breaking down a Mobile
  • Protocols in Chip Design
  • Chips Design Flow and Why Verification is needed?
  • Introduction to VIP
  • How VIP works in a Testbench
  • Q&A
Cadence Team 22-Jan-2026
4

Technical Online session on Component Library Creation and Management - Mastering Custom Parts in Altium Designer

The session covers the following topics :

  • This session is intended for advanced learners who already understand basic schematics and PCB design.
  • Understanding libraries, symbols, footprints, and why they matter
  • Creating schematic symbols and IPC-compliant footprints from scratch
  • Linking symbols and footprints to build integrated libraries
  • Using custom libraries in schematic projects for smoother design flow
Renesas-Altium Team 28-Jan-2026
5

Technical Online Session on "Renesas QuickConnect Studio Foundations: Create and Troubleshoot" by Renesas-Altium Team

The session covers the following topics :

  • Code Development & Upload: Develop, compile and upload your LED blink program using the QuickConnect Studio and install the Segger tool required for uploading the program to the microcontroller board.
  • Verification and Customization: Verify LED behaviour, experiment with customizing blink patterns and timing, and explore common troubleshooting techniques to ensure your project runs smoothly.
  • Local System Debugging: Learn how to display and manage print data for efficient system logging and real-time tracking.
Renesas-Altium Team 29-Jan-2026
6

Technical (Online) Session on Low Power Verification with CPF Using Cadence Conformal by Entuple Team

The Session details will be shared shortly

Entuple Team 30-Jan-2026
7

Technical Online Session on Formal Verification-Basics by Cadence Team

The Session details will be shared shortly

Cadence Team

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