C2S Programme aims to provide Participating Institutions with centralized access to EDA tools for designing FPGAs/ASICs/SoCs/IP Cores. This approach would enable optimal license utilization required by Institutions under C2S Programme for their design and development.

Furthermore, training on chip design methodology using EDA tools will be provided to Institutions new to chip development activities. This will be conducted via IEPs/training programs in coordination with the ChipIN Centre.

The process of VLSI chip development can be divided into VLSI design, Chip fabrication, Packaging, and Post Silicon Validation (Testing and Characterization). The VLSI chip fabrication process is highly sophisticated, expensive, and largely automated, with VLSI design being crucial to the chip's success. Proficient and efficient adoption of EDA tools for the VLSI design process is essential for successful tape outs and post-silicon chip development.

The following academic EDA Tools licenses are centrally available at the ChipIN Centre from various vendors.